Datasheet
LPC2377_78 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.1 — 16 October 2013 24 of 69
NXP Semiconductors
LPC2377/78
Single-chip 16-bit/32-bit microcontrollers
7.12 CAN controller and acceptance filters (LPC2378 only)
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.12.1 Features
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
• FullCAN messages can generate interrupts.
7.13 10-bit ADC
The LPC2377/78 contain one ADC. It is a single 10-bit successive approximation ADC
with eight channels.
7.13.1 Features
• 10-bit successive approximation ADC
• Input multiplexing among 8 pins
• Power-down mode
• Measurement range 0 V to V
i(VREF)
• 10-bit conversion time 2.44 s
• Burst conversion mode for single or multiple inputs
• Optional conversion on transition of input pin or Timer Match signal
• Individual result registers for each ADC channel to reduce interrupt overhead