Datasheet

LPC2387 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 16 October 2013 12 of 66
NXP Semiconductors
LPC2387
Single-chip 16-bit/32-bit MCU
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
50
[6]
I/O P2[13] — General purpose digital input/output pin.
I EINT3
— External interrupt 3 input.
O MCIDAT3 — Data line for SD/MMC interface.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
2
S-bus specification.
P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit.
The operation of port 3 pins depends upon the pin function selected via the pin
connect block. Pins 0 through 24, and 27 through 31 of this port are not
available.
P3[25]/MAT0[0]/
PWM1[2]
27
[1]
I/O P3[25] — General purpose digital input/output pin.
O MAT0[0] — Match output for Timer 0, channel 0.
O PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26]/MAT0[1]/
PWM1[3]
26
[1]
I/O P3[26] — General purpose digital input/output pin.
O MAT0[1] — Match output for Timer 0, channel 1.
O PWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit.
The operation of port 4 pins depends upon the pin function selected via the pin
connect block. Pins 0 through 27, 30, and 31 of this port are not available.
P4[28]/MAT2[0]/
TXD3
82
[1]
I/O P4[28] — General purpose digital input/output pin.
O MAT2[0] — Match output for Timer 2, channel 0.
O TXD3 — Transmitter output for UART3.
P4[29]/MAT2[1]/
RXD3
85
[1]
I/O P4[29] — General purpose digital input/output pin.
O MAT2[1] — Match output for Timer 2, channel 1.
I RXD3 — Receiver input for UART3.
TDO 1
[1][7]
O TDO — Test Data Out for JTAG interface.
TDI 2
[1][8]
I TDI — Test Data In for JTAG interface.
TMS 3
[1][8]
I TMS — Test Mode Select for JTAG interface.
TRST
4
[1][8]
I TRST — Test Reset for JTAG interface.
TCK 5
[1][7]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the
CPU clock (CCLK) for the JTAG interface to operate.
RTCK 100
[1][8]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET
is LOW enables ETM pins (P2[9:0]) to
operate as trace port after reset.
RSTOUT
14 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2387 being in
Reset state.
Note: This pin is available in LPC2387FBD100 devices only (LQFP100
package).
RESET
17
[9]
I External reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 22
[10][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 23
[10][11]
O Output from the oscillator amplifier.
RTCX1 16
[10][12]
I Input to the RTC oscillator circuit.
RTCX2 18
[10][12]
O Output from the RTC oscillator circuit.
Table 3. Pin description
…continued
Symbol Pin Type Description