Datasheet

LPC2387 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 16 October 2013 15 of 66
NXP Semiconductors
LPC2387
Single-chip 16-bit/32-bit MCU
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
7.2 On-chip flash programming memory
The LPC2387 incorporates a 512 kB flash memory system respectively. This memory
may be used for both code and data storage. Programming of the flash memory may be
accomplished in several ways. It may be programmed In System via the serial port
(UART0). The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field and
firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at SRAM speeds of 72 MHz.
7.3 On-chip SRAM
The LPC2387 includes a SRAM memory of 64 kB reserved for the ARM processor
exclusive use. This RAM may be used for code and/or data storage and may be accessed
as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller and an 16 kB SRAM
associated with the USB device can be used both for data and code storage, too. The
2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered
and retains the content in the absence of the main power supply.
7.4 Memory map
The LPC2387 memory map incorporates several distinct regions as shown in Figure 3.
In addition, the CPU interrupt vectors may be remapped to allow them to reside in either
flash memory (default), boot ROM, or SRAM (see Section 7.25.6
).