Datasheet

LPC2387 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 16 October 2013 31 of 66
NXP Semiconductors
LPC2387
Single-chip 16-bit/32-bit MCU
If power is supplied to the LPC2387 during Deep power-down mode, wake-up can be
caused by the RTC Alarm interrupt or by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2387 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
7.24.4.5 Power domains
The LPC2387 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the battery RAM.
On the LPC2387, I/O pads are powered by the 3.3 V (V
DD(3V3)
) pins, while the
V
DD(DCDC)(3V3)
pin powers the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Depending on the LPC2387 application, a design can use two power options to manage
power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
DD(3V3)
and V
DD(DCDC)(3V3)
pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
DD(3V3)
) and
a dedicated 3.3 V supply for the CPU (V
DD(DCDC)(3V3)
). Having the on-chip DC-to-DC
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
7.25 System control
7.25.1 Reset
Reset has four sources on the LPC2387: the RESET pin, the watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET
pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the wake-up timer (see description in Section 7.24.3 “
Wake-up timer”),
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the flash controller has completed its
initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.