Datasheet

Product data sheet Rev. 5.1 — 16 October 2013 32 of 66

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit MCU

7.25.2 Brownout detection

The LPC2387 includes 2-stage monitoring of the voltage on the V

DD(DCDC)(3V3)

pins. If this

voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt

Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the

VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register.

The second stage of low-voltage detection asserts Reset to inactivate the LPC2387 when

the voltage on the V

DD(DCDC)(3V3)

pins falls below 2.65 V. This Reset prevents alteration of

the flash as operation of the various elements of the chip would otherwise become

unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at

which point the power-on reset circuitry maintains the overall Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

7.25.3 Code security (Code Read Protection - CRP)

This feature of the LPC2387 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When

needed, CRP is invoked by programming a specific pattern into a dedicated flash location.

IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full flash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

7.25.4 AHB

The LPC2387 implements two AHBs in order to allow the Ethernet block to operate

without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and

16 kB SRAM primarily intended for use by the USB.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.