Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16/32-Bit 72 MHz I/O number 104

1. General description

The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with

real-time emulation that combines the microcontroller with 512

kB of embedded

high-speed flash memory. A 128-bit wide memory interface and a unique accelerator

architecture enable 32-bit code execution at the maximum clock rate. For critical

performance in interrupt service routines and DSP algorithms, this increases performance

up to 30

% over Thumb mode. For critical code size applications, the alternative 16-bit

Thumb mode reduces code by more than 30

% with minimal performance penalty.

The LPC2388 is ideal for multi-purpose serial communication applications. It incorporates

a 10/100 Ethernet Media Access Controller (MAC), USB device/host/OTG with 4

kB of

endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial

Ports (SSP), three I

C interfaces, an I

S interface, and an External Memory Controller

(EMC). This blend of serial communications interfaces combined with an on-chip 4

MHz

internal oscillator, SRAM of 64

kB, 16 kB SRAM for Ethernet, 16 kB SRAM for USB and

general purpose use, together with 2

kB battery powered SRAM make this device very

well suited for communication gateways and protocol converters. Various 32-bit timers, an

improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO

lines with up to 50 edge and up to four level sensitive external interrupt pins make these

microcontrollers particularly suitable for industrial control and medical systems.

2. Features

 ARM7TDMI-S processor, running at up to 72 MHz.

 Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM

local bus for high performance CPU access.

 64 kB of SRAM on the ARM local bus for high performance CPU access.

 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

 16 kB SRAM for general purpose DMA use also accessible by the USB.

 Dual Advanced High-performance Bus (AHB) system that provides for simultaneous

Ethernet DMA, USB DMA, and program execution from on-chip flash with no

contention between those functions. A bus bridge allows the Ethernet DMA to access

the other AHB subsystem.

 EMC provides support for static devices such as flash and SRAM as well as off-chip

memory mapped peripherals.

 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

LPC2388

Single-chip 16-bit/32-bit microcontroller; 512 kB flash with

ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit

ADC/DAC

Rev. 00.01 — 23 October 2007 Preliminary data sheet

Summary of content (57 pages)

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LPC2388 Single-chip 16-bit/32-bit microcontroller; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 00.01 — 23 October 2007 Preliminary data sheet 1. General description The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 512 kB of embedded high-speed flash memory.
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LPC2388 NXP Semiconductors Fast communication chip General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers. Serial Interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB bus. USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller.
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LPC2388 NXP Semiconductors Fast communication chip 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. Boundary scan for simplified board testing.
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LPC2388 NXP Semiconductors Fast communication chip 5.
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LPC2388 NXP Semiconductors Fast communication chip 6. Pinning information 109 144 6.1 Pinning 1 108 LPC2388FBD144 72 73 37 36 002aad333 Fig 2. LPC2388 pinning 6.2 Pin description Table 3. Pin description Symbol Pin P0[0] to P0[31] P0[0]/RD1/TXD/ SDA1 P0[1]/TD1/RXD3/ SCL1 66[1] 67[1] P0[2]/TXD0 141[1] P0[3]/RXD0 142[1] P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 116[1] Type Description I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P0[5]/ I2SRX_WS/ TD2/CAP2[1] 115[1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O TD2 — CAN2 transmitter output. I CAP2[1] — Capture input for Timer 2, channel 1. I/O P0[6] — General purpose digital input/output pin.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P0[14]/ USB_HSTEN2/ USB_CONNECT2/ SSEL1 48[1] I/O P0[14] — General purpose digital input/output pin. O USB_HSTEN2 — Host Enabled status for USB port 2. O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature. I/O SSEL1 — Slave Select for SSP1.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 13[2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I CAP3[0] — Capture input for Timer 3, channel 0.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P1[10]/ ENET_RXD1 129[1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. P1[14]/ ENET_RX_ER 128[1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. P1[15]/ ENET_REF_CLK 126[1] I/O P1[15] — General purpose digital input/output pin.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P1[25]/ USB_LS1/ USB_HSTEN1/ MAT1[1] 56[1] I/O P1[25] — General purpose digital input/output pin. O USB_LS1 — Low-speed status for USB port 1 (OTG transceiver). O USB_HSTEN1 — Host Enabled status for USB port 1. O MAT1[1] — Match output for Timer 1, channel 1. I/O P1[26] — General purpose digital input/output pin.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P2[2]/PWM1[3]/ CTS1/ PIPESTAT1 105[1] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O PIPESTAT1 — Pipeline Status, bit 1. I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P2[11]/EINT1/ MCIDAT1/ I2STX_CLK 75[6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. O MCIDAT1 — Data line for SD/MMC interface. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O P2[12] — General purpose digital input/output pin.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P3[25]/MAT0[0]/ PWM1[2] 39[1] I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/MAT0[1]/ PWM1[3] 38[1] I/O P3[26] — General purpose digital input/output pin. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description P4[24]/OE 127[1] I/O P4[24] — General purpose digital input/output pin. O OE — LOW active Output Enable signal. P4[25]/BLS0 124[1] I/O P4[25] — General purpose digital input/output pin. O BLS0 — LOW active Byte Lane select signal 0. I/O P4 [28] — General purpose digital input/output pin. O MAT2[0] — Match output for Timer 2, channel 0.
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LPC2388 NXP Semiconductors Fast communication chip Table 3. Pin description …continued Symbol Pin Type Description VDD(3V3) 41, 62, I 77, 102, 114, 138[11] 3.3 V supply voltage: This is the power supply voltage for the I/O ports. n.c. 21, 81, 98[12] I Leave these pins unconnected. VDD(DCDC)(3V3) 18, 60, 121[13] I 3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip DC-to-DC converter only. VDDA 14[14] I analog 3.
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LPC2388 NXP Semiconductors Fast communication chip The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2).
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LPC2388 NXP Semiconductors Fast communication chip The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. The LPC2388 provides a minimum of 100 000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2388 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits.
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LPC2388 NXP Semiconductors Fast communication chip 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 0xF000 0000 3.75 GB APB PERIPHERALS 3.5 GB 0xE000 0000 RESERVED ADDRESS SPACE 3.0 GB 0xC000 0000 0x8100 FFFF EXTERNAL MEMORY BANK 1 (64 kB) 0x8100 0000 0x8000 FFFF EXTERNAL MEMORY BANK 0 (64 kB) 0x8000 0000 2.
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LPC2388 NXP Semiconductors Fast communication chip FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device.
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LPC2388 NXP Semiconductors Fast communication chip • Static memory features include: – Asynchronous page mode read – Programmable Wait States (WST) – Bus turnaround delay – Output enable and write enable delays – Extended wait 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions.
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LPC2388 NXP Semiconductors Fast communication chip • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.9 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers.
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LPC2388 NXP Semiconductors Fast communication chip via the EMC, as well as the SRAM located on another AHB, if it is not being used by the USB block. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.10.
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LPC2388 NXP Semiconductors Fast communication chip 7.11 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The Host Controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host Controller. The LPC2388 USB interface includes a device, Host, and OTG Controller.
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LPC2388 NXP Semiconductors Fast communication chip 7.11.3 USB OTG Controller USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the Host Controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.11.3.
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LPC2388 NXP Semiconductors Fast communication chip 7.13 10-bit ADC The LPC2388 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • • • • • • • • 10-bit successive approximation ADC Input multiplexing among 8 pins Power-down mode Measurement range 0 V to Vi(VREF) 10-bit conversion time ≥ 2.
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LPC2388 NXP Semiconductors Fast communication chip • UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2388 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer.
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LPC2388 NXP Semiconductors Fast communication chip • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.19 I2C-bus serial I/O controllers The LPC2388 contains three I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA).
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LPC2388 NXP Semiconductors Fast communication chip • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz ((16, 22.05, 32, 44.1, 48) kHz). • • • • Configurable word select period in master mode (separately for I2S input and output). Two 8 word FIFO data buffers are provided, one for transmit and one for receive. Generates interrupt requests when buffer levels cross a programmable boundary. Two DMA requests, controlled by programmable buffer levels.
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LPC2388 NXP Semiconductors Fast communication chip The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match.
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LPC2388 NXP Semiconductors Fast communication chip 7.23 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 7.23.1 Features • Internally resets chip if not periodically reloaded. • Debug mode.
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LPC2388 NXP Semiconductors Fast communication chip • An alarm output pin is included to assist in waking up from Power-down mode, or when the chip has had power removed to all functions except the RTC and Battery RAM. • Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. • 2 kB data SRAM powered by VBAT. • RTC and Battery RAM power supply is isolated from the rest of the chip. 7.25 Clocking and power control 7.25.
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LPC2388 NXP Semiconductors Fast communication chip Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input.
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LPC2388 NXP Semiconductors Fast communication chip 7.25.4.1 Idle mode In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.25.4.
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LPC2388 NXP Semiconductors Fast communication chip The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.
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LPC2388 NXP Semiconductors Fast communication chip 7.26.3 Code security (Code Read Protection - CRP) This feature of the LPC2388 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection.
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LPC2388 NXP Semiconductors Fast communication chip 7.27 Emulation and debugging The LPC2388 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself. 7.27.
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LPC2388 NXP Semiconductors Fast communication chip 7.27.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2388 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory.
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LPC2388 NXP Semiconductors Fast communication chip 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.6 V 3.0 3.6 V −0.5 +4.6 V −0.5 +4.6 V −0.5 +4.6 V −0.5 +5.1 V [2] −0.5 +6.0 V other I/O pins [2][3] −0.5 VDD(3V3) + 0.5 V VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 V) VDDA analog 3.
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LPC2388 NXP Semiconductors Fast communication chip 9. Static characteristics Table 5. Static characteristics Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 V) 3.0 3.3 3.6 V VDDA analog 3.3 V pad supply voltage 3.0 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT 2.0 3.3 3.
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LPC2388 NXP Semiconductors Fast communication chip Table 5. Static characteristics …continued Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit CCLK = 10 MHz - 15 - mA CCLK = 72 MHz - 63 - mA CCLK = 10 MHz - 21 - mA CCLK = 72 MHz - 92 - mA CCLK = 10 MHz - 27 - mA CCLK = 72 MHz - 125 - mA - 150 Conditions IDD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) = 3.
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LPC2388 NXP Semiconductors Fast communication chip Table 5. Static characteristics …continued Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDI differential input sensitivity |(D+) − (D−)| 0.2 - - V VCM differential common mode voltage range includes VDI range 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage 0.8 - 2.
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LPC2388 NXP Semiconductors Fast communication chip [1] Conditions: VSSA = 0 V, VDDA = 3.3 V. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 4.
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LPC2388 NXP Semiconductors Fast communication chip offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Via (LSBideal) offset error EO 1 LSB = VDDA − VSSA 1024 002aab136 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC2388 NXP Semiconductors Fast communication chip LPC2378 20 kΩ AD0[y] AD0[y]SAMPLE 3 pF Rvsi 5 pF VEXT VSS 002aac610 Fig 5. Suggested ADC interface - LPC2388 AD0[y] pin LPC2388_0 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.
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LPC2388 NXP Semiconductors Fast communication chip 10. Dynamic characteristics Table 7. Dynamic characteristics of USB pins (full-speed) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3),unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.
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LPC2388 NXP Semiconductors Fast communication chip 10.1 Timing VDD − 0.5 V 0.45 V 0.2VDD + 0.9 V 0.2VDD − 0.1 V tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 VDD = 1.8 V. Fig 6. External clock timing tPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × tPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 7.
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LPC2388 NXP Semiconductors Fast communication chip 11. Application information 11.1 Suggested USB interface solutions VDD(3V3) USB_UP_LED USB_CONNECT LPC23XX soft-connect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB_D− USB-B connector RS = 33 Ω VSS 002aac578 Fig 9. LPC2388 USB interface on a self-powered device VDD(3V3) R2 LPC23XX USB_UP_LED R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSS 002aac579 Fig 10.
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LPC2388 NXP Semiconductors Fast communication chip VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND R4 R5 DP 33 Ω DM 33 Ω ISP1301 R6 VSS SCL USB_SCL1 Mini-AB connector SDA USB_SDA1 INT_N USB_INT1 USB_D+1 USB_D−1 VDD USB_UP_LED1 LPC2388 R7 5V VDD IN USB_PPWR2 ENA LM3526-L OUTA FLAGA USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− 15 kΩ 15 kΩ USB-A connector VSS VDD USB_UP_LED2 R8 002aad336 Fig 11.
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LPC2388 NXP Semiconductors Fast communication chip VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 USB_RX_DM1 VP VBUS VM ID VDD ISP1301 LPC2388 ADR/PSW DP 33 Ω DM 33 Ω USB MINI-AB connector VSS SPEED SUSPEND USB_SCL1 SCL SDA USB_SDA1 INT_N USB_INT1 VDD USB_UP_LED1 002aad337 Fig 12. LPC2388 USB OTG port configuration: VP_VM mode LPC2388_0 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.
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LPC2388 NXP Semiconductors Fast communication chip VDD USB_UP_LED1 VSS USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA 5V IN LM3526-L OUTA LPC2388 VDD USB_UP_LED2 VDD USB_CONNECT2 VSS USB_D+2 33 Ω D+ USB_D−2 33 Ω D− VBUS USB-B connector VBUS 002aad335 Fig 13. LPC2388 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2388_0 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 00.
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LPC2388 NXP Semiconductors Fast communication chip VDD USB_UP_LED1 VSS USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA OUTA 5V IN LPC2388 USB_PPWR2 LM3526-L ENB VDD OUTB FLAGB USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− 15 kΩ USB-A connector VSS 15 kΩ VDD USB_UP_LED2 002aad338 Fig 14. LPC2388 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2388_0 Preliminary data sheet © NXP B.V.
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LPC2388 NXP Semiconductors Fast communication chip 12. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.
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LPC2388 NXP Semiconductors Fast communication chip 13. Abbreviations Table 9.
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LPC2388 NXP Semiconductors Fast communication chip 14. Revision history Table 10. Revision history Document ID Release date LPC2388_0.01 Data sheet status LPC2388_0 Preliminary data sheet Change notice Supersedes © NXP B.V. 2007. All rights reserved. Rev. 00.
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LPC2388 NXP Semiconductors Fast communication chip 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC2388 NXP Semiconductors Fast communication chip 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC2388 NXP Semiconductors Fast communication chip 15.2 15.3 15.4 16 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .