Datasheet

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007 15 of 57
NXP Semiconductors
LPC2388
Fast communication chip
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O I
2
C-bus 400 kHz specification compatible pad. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I
2
C-bus is floating and does not disturb the I
2
C lines.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[8] Pad provides special analog functionality.
[9] Pad provides special analog functionality.
[10] Pad provides special analog functionality.
[11] Pad provides special analog functionality.
[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
7. Functional description
7.1 Architectural overview
The LPC2388 microcontroller consists of an ARM7TDMI-S CPU with emulation support,
the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip
memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external
memory, and the AMBA APB for connection to other on-chip peripheral functions. The
microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte
order.
The LPC2388 implements two AHB buses in order to allow the Ethernet block to operate
without interference caused by other system activity. The primary AHB, referred to as
AHB1, includes the VIC, GPDMA controller, and EMC.
V
DD(3V3)
41, 62,
77, 102,
114,
138
[11]
I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
n.c. 21, 81,
98
[12]
I Leave these pins unconnected.
V
DD(DCDC)(3V3)
18, 60,
121
[13]
I 3.3 V DC-to-DC converter supply voltage: This is the power supply for the on-chip
DC-to-DC converter only.
V
DDA
14
[14]
I analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
DD(3V3)
but should be isolated to minimize noise and error. This voltage is used to
power the ADC and DAC.
VREF 17
[14]
I ADC reference: This should be nominally the same voltage as V
DD(3V3)
but should
be isolated to minimize noise and error. The level on this pin is used as a reference
for ADC and DAC.
VBAT 27
[14]
I RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
Table 3. Pin description …continued
Symbol Pin Type Description