Datasheet

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007 17 of 57
NXP Semiconductors
LPC2388
Fast communication chip
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at SRAM speeds of 72
MHz.
The LPC2388 provides a minimum of 100 000 write/erase cycles and 20 years of data
retention.
7.3 On-chip SRAM
The LPC2388 includes a SRAM memory of 64 kB reserved for the ARM processor
exclusive use. This RAM may be used for code and/or data storage and may be accessed
as 8
bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM
associated with the USB device can be used both for data and code storage, too. The
2
kB RTC can be used for data storage only. The RTC SRAM is battery powered and
retains the content in the absence of the main power supply.
7.4 Memory map
The LPC2388 memory map incorporates several distinct regions as shown in Figure 3.
In addition, the CPU interrupt vectors may be remapped to allow them to reside in either
flash memory (default), boot ROM, or SRAM (see
Section 7.26.6).