Datasheet

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007 33 of 57
NXP Semiconductors
LPC2388
Fast communication chip
7.25.4.1 Idle mode
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.25.4.2 Sleep mode
In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The
32
kHz RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
The Sleep mode can be terminated and normal operation resumed by either a Reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Sleep mode reduces chip power consumption to a
very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.
On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the
code execution and peripherals activities will resume after 4 cycles expire. If the main
external oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
7.25.4.3 Power-down mode
Power-down mode does everything that Sleep mode does, but also turns off the IRC
oscillator and the flash memory. This saves more power, but requires waiting for
resumption of flash operation before execution of code or data access in the flash memory
can be accomplished.
On the wake-up of power-down mode, if the IRC was used before entering power-down
mode, it will take IRC 60
μs to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then counts 4
MHz IRC clock cycles to make the 100 μs flash start-up
time. When it times out, access to the flash will be allowed. The customers need to
reconfigure the PLL and clock dividers accordingly.
7.25.4.4 Power domains
The LPC2388 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the Battery RAM.
On the LPC2388, I/O pads are powered by the 3.3 V (V
DD(3V3)
) pins, while the
V
DD(DCDC)(3V3)
pin powers the on-chip DC-to-DC converter which in turn provides power to
the CPU and most of the peripherals.
Depending on the LPC2388 application, a design can use two power options to manage
power consumption.