Datasheet

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007 45 of 57
NXP Semiconductors
LPC2388
Fast communication chip
10. Dynamic characteristics
[1] Characterized but not implemented as production test. Guaranteed by design.
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance C
b
in pF, from 10 pF to 400 pF.
Table 7. Dynamic characteristics of USB pins (full-speed)
C
L
= 50 pF; R
pu
= 1.5 k Ω on D+ to V
DD(3V3)
,unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time 10 % to 90 % 8.5 - 13.8 ns
t
f
fall time 10 % to 90 % 7.7 - 13.7 ns
t
FRFM
differential rise and fall time
matching
t
r
/ t
f
- - 109 %
V
CRS
output signal crossover voltage 1.3 - 2.0 V
t
FEOPT
source SE0 interval of EOP see Figure 7 160 - 175 ns
t
FDEOP
source jitter for differential transition
to SE0 transition
see Figure 7 −2 - +5 ns
t
JR1
receiver jitter to next transition −18.5 - +18.5 ns
t
JR2
receiver jitter for paired transitions 10 % to 90 % −9 - +9 ns
t
EOPR1
EOP width at receiver must reject as
EOP; see
Figure 7
[1]
40 - - ns
t
EOPR2
EOP width at receiver must accept as
EOP; see
Figure 7
[1]
82 - - ns
Table 8. Dynamic characteristics
T
amb
= − 40 ° C to +85 ° C for commercial applications; V
DD(3V3)
over specified ranges.
[1]
Symbol Parameter Conditions Min Typ
[2]
Max Unit
External clock
f
osc
oscillator frequency 1 - 24 MHz
T
cy(clk)
clock cycle time 42 - 1000 ns
t
CHCX
clock HIGH time T
cy(clk)
× 0.4 - - ns
t
CLCX
clock LOW time T
cy(clk)
× 0.4 - - ns
t
CLCH
clock rise time - - 5 ns
t
CHCL
clock fall time - - 5 ns
I
2
C-bus pins (P0[27] and P0[28])
t
f(o)
output fall time V
IH
to V
IL
20 + 0.1 × C
b
[3]
- - ns
SSP interface
t
su(SPI_MISO)
SPI_MISO set-up time T
amb
= 25 °C;
measured in
SPI Master
mode; see
Figure 8
- 11 - ns