Datasheet

LPC2388_0 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 00.01 — 23 October 2007 46 of 57
NXP Semiconductors
LPC2388
Fast communication chip
10.1 Timing
V
DD
= 1.8 V.
Fig 6. External clock timing
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907
0.2V
DD
+ 0.9 V
0.2V
DD
− 0.1 V
V
DD
− 0.5 V
0.45 V
Fig 7. Differential data-to-EOP transition skew and EOP width
002aab561
t
PERIOD
differential
data lines
crossover point
source EOP width: t
FEOPT
receiver EOP width: t
EOPR1
, t
EOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × t
PERIOD
+ t
FDEOP
Fig 8. MISO line set-up time in SSP Master mode
t
su(SPI_MISO)
SCK
shifting edges
MOSI
MISO
002aad326
sampling edges