Datasheet
LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 24 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
P4[31]/CS1 193
[1]
A4
[1]
I/O P4[31] — General purpose digital input/output pin.
O CS1
— LOW active Chip Select 1 signal.
ALARM 37
[7]
N1
[7]
O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH
when a RTC alarm is generated.
USB_D252U1I/OUSB_D2 — USB port 2 bidirectional D line.
DBGEN 9
[1][8]
F4
[1][8]
I DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO 2
[1][9]
D3
[1][9]
O TDO — Test data out for JTAG interface.
TDI 4
[1][8]
C2
[1][8]
I TDI — Test data in for JTAG interface.
TMS 6
[1][8]
E3
[1][8]
I TMS — Test Mode Select for JTAG interface.
TRST
8
[1][8]
D1
[1][8]
I TRST — Test Reset for JTAG interface.
TCK 10
[1][9]
E2
[1][9]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK 206
[1][8]
C3
[1][8]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins
(P2[9:0]) to operate as Trace port after reset.
RSTOUT
29 K3 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates
LPC2420/2460 being in Reset state.
RESET
35
[10]
M2
[10]
I external reset input: A LOW on this pin resets the device, causing
I/O ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 44
[7][11]
M4
[7][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 46
[7][11]
N4
[7][11]
O Output from the oscillator amplifier.
RTCX1 34
[7][12]
K2
[7][12]
I Input to the RTC oscillator circuit.
RTCX2 36
[7][12]
L2
[7][12]
O Output from the RTC oscillator circuit.
V
SSIO
33, 63,
77, 93,
114,
133, 148,
169, 189,
200
[7]
L3, T5,
R9,
P12,
N16,
H14,
E15, A12,
B6, A2
[7]
I ground: 0 V reference for the digital I/O pins.
V
SSCORE
32, 84,
172
[7]
K4, P10,
D12
[7]
I ground: 0 V reference for the core.
V
SSA
22
[7]
J2
[7]
I analog ground: 0 V reference. This should nominally be the same
voltage as V
SSIO
/V
SSCORE
, but should be isolated to minimize noise
and error.
V
DD(3V3)
15, 60,
71, 89,
112,
125, 146,
165,
181,
198
[7]
G3,
P6, P8,
U13,
P17,
K16,
C17,
B13,
C9,
D7
[7]
I 3.3 V supply voltage: This is the power supply voltage for the I/O
ports.
n.c. 30, 117,
141
[7]
J4, L14,
G14
[7]
I not connected pins: These pins must be left unconnected (floating).
Table 4. Pin description
…continued
Symbol Pin Ball Type Description