Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 180 (12x12) 16/32-Bit 72 MHz I/O number 136

1. General description

NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit

ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and

embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This

flash memory includes a special 128-bit wide memory interface and accelerator

architecture that enables the CPU to execute sequential instructions from flash memory at

the maximum 72 MHz system clock rate. This feature is available only on the LPC2000

ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and

16-bit Thumb instructions. Support for the two instruction sets means engineers can

choose to optimize their application for either performance or code size at the sub-routine

level. When the core executes instructions in Thumb state it can reduce code size by

more than 30 % with only a small loss in performance while executing instructions in ARM

state maximizes core performance.

The LPC2458 microcontroller is ideal for multi-purpose communication applications. It

incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed

Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area

Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I

interfaces, and an I

S interface. Supporting this collection of serial communications

interfaces are the following feature components; an on-chip 4 MHz internal precision

oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for

Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an

External Memory Controller (EMC). These features make this device optimally suited for

communication gateways and protocol converters. Complementing the many serial

communication controllers, versatile clocking capabilities, and memory features are

various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external

interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins

to the hardware based Vector Interrupt Controller (VIC) that means these external inputs

can generate edge-triggered interrupts. All of these features make the LPC2458

particularly suitable for industrial control and medical systems.

2. Features and benefits

 ARM7TDMI-S processor, running at up to 72 MHz.

 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM

local bus for high performance CPU access.

 98 kB on-chip SRAM includes:

 64 kB of SRAM on the ARM local bus for high performance CPU access.

 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

LPC2458

Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN,

ISP/IAP, USB 2.0 device/host/OTG, external memory interface

Rev. 4.1 — 15 October 2013 Product data sheet

Summary of content (81 pages)

PAGE 1
LPC2458 Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 4.1 — 15 October 2013 Product data sheet 1. General description NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory.
PAGE 2
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro             LPC2458 Product data sheet  16 kB SRAM for general purpose DMA use also accessible by the USB.  2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain. Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.
PAGE 3
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro  Two independent power domains allow fine tuning of power consumption based on needed features.  Each peripheral has its own clock divider for further power saving. These dividers help reduce active power by 20 % to 30 %.  Brownout detect with separate thresholds for interrupt and forced reset.  On-chip power-on reset.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
PAGE 4
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 5.
PAGE 5
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 6. Pinning information 6.1 Pinning ball A1 index area LPC2458 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aad094 Transparent top view Fig 2. Table 3.
PAGE 6
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 3.
PAGE 7
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 3.
PAGE 8
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 6.2 Pin description Table 4. Pin description Symbol Ball P0[0] to P0[31] P0[0]/RD1/ TXD3/SDA1 P0[1]/TD1/RXD3/ SCL1 M10[1] N11[1] Type Description I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect block. I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input.
PAGE 9
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] A13[1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3.
PAGE 10
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P0[17]/CTS1/ MISO0/MISO J12[1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0.
PAGE 11
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P0[26]/AD0[3]/ AOUT/RXD3 D1[2][3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — D/A converter output.
PAGE 12
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5] C13[1] I/O P1[7] — General purpose digital input/output pin. I ENET_COL — Ethernet Collision detect (MII interface). I/O MCIDAT1 — Data line 1 for SD/MMC interface.
PAGE 13
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0 K6[1] I/O P1[20] — General purpose digital input/output pin. O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
PAGE 14
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P1[30]/ USB_PWRD2/ VBUS/AD0[4] K3[2] I/O P1[30] — General purpose digital input/output pin. I USB_PWRD2 — Power Status for USB port 2. I VBUS — Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. P1[31]/ USB_OVRCR2/ SCK1/AD0[5] K2[2] P2[0] to P2[31] I AD0[4] — A/D converter 0, input 4.
PAGE 15
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P2[7]/RD2/ RTS1/ TRACEPKT2 G11[1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. O RTS1 — Request to Send output for UART1. P2[8]/TD2/ TXD2/ TRACEPKT3 G14[1] P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0 H11[1] P2[10]/EINT0 M13[6] O TRACEPKT2 — Trace Packet, bit 2. I/O P2[8] — General purpose digital input/output pin.
PAGE 16
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P2[20]/DYCS0 P6[1] I/O P2[20] — General purpose digital input/output pin. O DYCS0 — SDRAM chip select 0. P2[21]/DYCS1 N8[1] I/O P2[21] — General purpose digital input/output pin. O DYCS1 — SDRAM chip select 1. P2[24]/ CKEOUT0 P1[1] I/O P2[24] — General purpose digital input/output pin. O CKEOUT0 — SDRAM clock enable 0.
PAGE 17
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P3[12]/D12 A1[1] I/O P3[12] — General purpose digital input/output pin. I/O D12 — External memory data line 12. P3[13]/D13 C1[1] I/O P3[13] — General purpose digital input/output pin. I/O D13 — External memory data line 13. P3[14]/D14 F1[1] I/O P3[14] — General purpose digital input/output pin. I/O D14 — External memory data line 14.
PAGE 18
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P4[8]/A8 J11[1] I/O P4[8] — General purpose digital input/output pin. I/O A8 — External memory address line 8. P4[9]/A9 H12[1] I/O P4[9] — General purpose digital input/output pin. I/O A9 — External memory address line 9. P4[10]/A10 G12[1] I/O P4[10] — General purpose digital input/output pin. I/O A10 — External memory address line 10.
PAGE 19
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description P4[31]/CS1 E7[1] I/O P4[31] — General purpose digital input/output pin. O CS1 — LOW active Chip Select 1 signal. ALARM H5[7] O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. USB_D2 N2 I/O USB_D2 — USB port 2 bidirectional D line. DBGEN E5[1][8] I DBGEN — JTAG interface control signal.
PAGE 20
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Ball Type Description VDDA F2[18] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. VREF G2[18] I ADC reference: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error.
PAGE 21
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2).
PAGE 22
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.3 On-chip SRAM The LPC2458 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the second AHB can be used both for data and code storage. The 2 kB RTC SRAM can be used for data storage only.
PAGE 23
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 0xFFFF FFFF 4.0 GB AHB PERIPHERALS 0xF000 0000 3.75 GB APB PERIPHERALS 0xE000 0000 0xDFFF FFFF 3.5 GB RESERVED ADDRESS SPACE 0xC000 0000 0xBFFF FFFF EXTERNAL STATIC AND DYNAMIC MEMORY 2.0 GB 0x8000 0000 0x7FFF FFFF BOOT ROM AND BOOT FLASH (BOOT FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.
PAGE 24
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority.
PAGE 25
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • Static memory features include: – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Two chip selects for synchronous memory and two chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software.
PAGE 26
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • One AHB master for transferring data. This interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • Internal four-word FIFO per channel.
PAGE 27
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.10 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity.
PAGE 28
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.11 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The Host Controller allocates the USB bandwidth to attached devices through a token-based protocol.
PAGE 29
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • Two downstream ports. • Supports per-port power switching. 7.11.3 USB OTG Controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the Host Controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality.
PAGE 30
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.13 10-bit ADC The LPC2458 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • • • • • • • • 10-bit successive approximation ADC Input multiplexing among 8 pins Power-down mode Measurement range 0 V to Vi(VREF) 10-bit conversion time  2.
PAGE 31
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2458 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer.
PAGE 32
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.19 I2C-bus serial I/O controller The LPC2458 contains three I2C-bus controllers.
PAGE 33
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • • • • Configurable word select period in master mode (separately for I2S input and output).
PAGE 34
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2458. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
PAGE 35
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses.
PAGE 36
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power is removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation. 7.24.1 Features • Measures the passage of time to maintain a calendar and clock.
PAGE 37
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.25.2 for additional information. 7.25.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.25.
PAGE 38
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.25.4 Power control The LPC2458 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.
PAGE 39
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.25.4.4 Deep power-down mode Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off.
PAGE 40
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.26 System control 7.26.1 Reset Reset has four sources on the LPC2458: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.25.
PAGE 41
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.26.4 AHB The LPC2458 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM.
PAGE 42
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. 7.27.
PAGE 43
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +5.1 V [2] 0.5 +6.0 V other I/O pins [2][3] 0.5 VDD(3V3) + 0.5 V per supply pin [4] - 100 mA - 100 mA 65 +150 C - 1.
PAGE 44
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
PAGE 45
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 10. Static characteristics Table 9. Static characteristics Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 V) 3.0 3.3 3.6 V VDDA analog 3.3 V pad supply voltage 3.0 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT 2.0 3.
PAGE 46
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 9. Static characteristics …continued Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
PAGE 47
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 9. Static characteristics …continued Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 1.8 1.95 V Vo(RTCX2) output voltage on pin RTCX2 0.5 1.8 1.
PAGE 48
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 10.1 Power-down mode 002aae049 4 IDD(IO) (μA) 2 VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V 0 −2 −4 −40 −15 10 35 60 85 temperature (°C) Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C. Fig 4. I/O maximum supply current IDD(IO) versus temperature in Power-down mode 002aae050 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C. Fig 5.
PAGE 49
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 002aae051 800 IDD(DCDC)pd(3v3) (μA) 600 400 VDD(DCDC)(3V3) = 3.3 V 200 0 −40 VDD(DCDC)(3V3) = 3.0 V −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C. Fig 6. Total DC-to-DC converter supply current IDD(DCDC)pd(3V3) at different temperatures in Power-down mode 10.2 Deep power-down mode 002aae046 300 IDD(IO) (μA) 200 100 VDD(3V3) = 3.3 V VDD(3V3) = 3.
PAGE 50
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 002aae047 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C Fig 8. RTC battery maximum supply current IBAT versus temperature in Deep power-down mode 002aae048 100 IDD(DCDC)dpd(3v3) (μA) 80 60 VDD(DCDC)(3V3) = 3.3 V 40 VDD(DCDC)(3V3) = 3.0 V 20 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C. Fig 9.
PAGE 51
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(3V3) = 3.3 V; standard port pins. Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(3V3) = 3.3 V; standard port pins. Fig 11.
PAGE 52
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 11. Dynamic characteristics Table 10. Dynamic characteristics Tamb = 40 C to +85 C for commercial applications; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Typ[2] Min Max Unit External clock fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.
PAGE 53
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.1 Internal oscillators Table 11. Dynamic characteristic: Internal oscillators Tamb = 40 C to +85 C; 3.0 V  VDD(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Max Unit [1] Parameters are valid over operating temperature range unless otherwise specified.
PAGE 54
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.4 Flash memory Table 14. Dynamic characteristics of flash Tamb = 40 C to +85 C, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.
PAGE 55
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors LPC2458 Product data sheet 11.5 Static external memory interface Table 15.
PAGE 56
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Symbol Parameter Conditions Min Typ Max Unit 0.78 + Tcy(CCLK) 2.54 + Tcy(CCLK) 5.
PAGE 57
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.6 Dynamic external memory interface Table 16. Dynamic characteristics: Dynamic external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, EMC Dynamic Read Config Register = 0x0 (RD = 00) Symbol Parameter Conditions Min Typ Max Unit 1.05 1.76 ns Common chip select valid delay time [1] - th(S) chip select hold time [1] 0.1 1.
PAGE 58
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 17. Dynamic characteristics: Dynamic external memory interface CL = 30 pF on all pins, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.3 V, EMC Dynamic Read Config Register = 0x1 (RD = 01), Tcy(CCLK) = 1/CCLK Symbol Parameter Conditions Min Typ Max Unit Common td(SV) chip select valid delay time [1] - 3 + Tcy(CCLK) 1.
PAGE 59
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.7 Timing tCSLAV tCSHOEH CS addr tam th(D) data tCSLOEL tOELAV tOEHANV tOELOEH OE tCSHBLSH tBLSLAV BLS 002aad955 Fig 13. External memory read access CS tCSLAV tCSLWEL tWELWEH tBLSLBLSH BLS/WE tWEHANV tCSLBLSL tWELDV tBLSHANV addr tCSLDV tWEHDNV tBLSHDNV data OE 002aad956 Fig 14. External memory write access LPC2458 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.
PAGE 60
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 15. Differential data-to-EOP transition skew and EOP width shifting edges SCK sampling edges MOSI MISO tsu(SPI_MISO) 002aad326 Fig 16.
PAGE 61
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 12. ADC electrical characteristics Table 18. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz.
PAGE 62
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = Vi(VREF) − VSSA 1024 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
PAGE 63
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro LPC2XXX 20 kΩ AD0[y] AD0[y]SAMPLE 3 pF Rvsi 5 pF VEXT VSSIO, VSSCORE 002aad586 Fig 19. Suggested ADC interface - LPC2458 AD0[y] pin LPC2458 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 15 October 2013 © NXP B.V. 2013. All rights reserved.
PAGE 64
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 13. DAC electrical characteristics Table 19. DAC electrical characteristics VDDA = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter ED Min Typ Max Unit differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.
PAGE 65
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 14. Application information 14.1 Suggested USB interface solutions VDD(3V3) USB_UP_LED USB_CONNECT LPC24XX soft-connect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB_D− USB-B connector RS = 33 Ω VSSIO, VSSCORE 002aad587 Fig 20. LPC2458 USB interface on a self-powered device VDD(3V3) R2 LPC24XX USB_UP_LED R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSSIO, VSSCORE 002aad588 Fig 21.
PAGE 66
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND R4 R5 ISP1302 DP 33 Ω DM 33 Ω R6 VSSIO, VSSCORE SCL USB_SCL1 Mini-AB connector SDA USB_SDA1 USB_INT1 INT_N USB_D+1 USB_D−1 VDD USB_UP_LED1 LPC24XX R7 5V VDD IN USB_PPWR2 ENA LM3526-L OUTA FLAGA USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− 15 kΩ 15 kΩ USB-A connector VSSIO, VSSCORE VDD USB_UP_LED2 R8 002aad589
PAGE 67
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 USB_RX_DM1 VP VBUS VM ID VDD ISP1302 LPC24XX ADR/PSW SPEED DP 33 Ω DM 33 Ω USB MINI-AB connector VSSIO, VSSCORE SUSPEND USB_SCL1 SCL USB_SDA1 SDA INT_N USB_INT1 VDD USB_UP_LED1 002aad590 Fig 23.
PAGE 68
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA 5V IN LM3526-L OUTA LPC24XX VDD USB_UP_LED2 VDD USB_CONNECT2 VSSIO, VSSCORE USB_D+2 33 Ω D+ USB_D−2 33 Ω D− VBUS USB-B connector VBUS 002aad595 Fig 24.
PAGE 69
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA OUTA 5V IN LPC24XX USB_PPWR2 LM3526-L ENB VDD OUTB FLAGB USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− 15 kΩ USB-A connector VSSIO, VSSCORE 15 kΩ VDD USB_UP_LED2 002aad596 Fig 25. LPC2458 USB OTG port configuration: USB port 1 host, USB port 2 host 14.
PAGE 70
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 26), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 27 and in Table 20 and Table 21.
PAGE 71
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 21. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 20 MHz to 25 MHz 14.
PAGE 72
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain.
PAGE 73
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 14.6 Reset pin configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 30. Reset pin configuration LPC2458 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 15 October 2013 © NXP B.V. 2013. All rights reserved.
PAGE 74
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 15. Package outline TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 A B D ball A1 index area E A2 A A1 detail X e1 e 1/2 e ∅v ∅w b M M C C A B C y y1 C P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 X 14 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 v w y y1 1.20 1.06 0.
PAGE 75
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 16. Soldering Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 0.80 0.400 0.400 0.550 Hx Hy 12.575 12.575 sot570-3_fr Fig 32.
PAGE 76
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 17. Abbreviations Table 23.
PAGE 77
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 18. Revision history Table 24. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2458 v.4.1 20131015 Product data sheet - LPC2458 v.4 Modifications: • • • • LPC2458 v.4 Modifications: Table 4 “Pin description”, Table note 6: Changed glitch filter spec from 5 ns to 10 ns. Table 10 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.
PAGE 78
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 79
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 80
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 81
LPC2458 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.5 11.6 11.7 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Static external memory interface . . . . . . . . . . Dynamic external memory interface . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC electrical characteristics . . . . . . . . . . . . DAC electrical characteristics . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . .