Datasheet

Product data sheet Rev. 6.2 — 11 January 2013 45 of 85

NXP Semiconductors

LPC2468

Single-chip 16-bit/32-bit micro

7.26.4 AHB

The LPC2468 implements two AHB in order to allow the Ethernet block to operate without

interference caused by other system activity. The primary AHB, referred to as AHB1,

includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB

SRAM.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the

GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters

with access to AHB2 are the ARM7 and the Ethernet block.

7.26.5 External interrupt inputs

The LPC2468 includes up to 68 edge sensitive interrupt inputs combined with up to four

level sensitive external interrupt inputs as selectable pin functions. The external interrupt

inputs can optionally be used to wake up the processor from Power-down mode.

7.26.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear at the

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot

ROM, the SRAM, or external memory. This allows code running in different memory

spaces to have control of the interrupts.

7.27 Emulation and debugging

The LPC2468 support emulation and debugging via a JTAG serial port. A trace port allows

tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface

peripherals residing on other pins are available during the development and debugging

phase as they are when the application is run in the embedded system itself.

7.27.1 EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the target

system requires a host computer running the debugger software and an EmbeddedICE

protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug

Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present

on the target system.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC

allows a program running on the target to communicate with the host debugger or another

separate host without stopping the program flow or even entering the debug state. The

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.