Datasheet

LPC2470 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 16 October 2013 24 of 91
NXP Semiconductors
LPC2470
Flashless 16-bit/32-bit microcontroller
DBGEN 9
[1][16]
F4
[1][16]
I DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO 2
[1][17]
D3
[1][17]
O TDO — Test Data Out for JTAG interface.
TDI 4
[1][16]
C2
[1][16]
I TDI — Test Data In for JTAG interface.
TMS 6
[1][16]
E3
[1][16]
I TMS — Test Mode Select for JTAG interface.
TRST
8
[1][16]
D1
[1][16]
I TRST — Test Reset for JTAG interface.
TCK 10
[1][17]
E2
[1][17]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK 206
[1][16]
C3
[1][16]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET
is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT
29 K3 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2470
being in Reset state.
RESET
35
[12]
M2
[12]
I external reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 44
[13][14]
M4
[13][14]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 46
[13][14]
N4
[13][14]
O Output from the oscillator amplifier.
RTCX1 34
[13][15]
K2
[13][15]
I Input to the RTC oscillator circuit.
RTCX2 36
[13][15]
L2
[13][15]
O Output from the RTC oscillator circuit.
V
SSIO
33, 63,
77, 93,
114,
133,
148,
169,
189,
200
[13]
L3, T5,
R9, P12,
N16,
H14,
E15,
A12, B6,
A2
[13]
I ground: 0 V reference for the digital IO pins.
V
SSCORE
32, 84,
172
[13]
K4, P10,
D12
[13]
I ground: 0 V reference for the core.
V
SSA
22
[13]
J2
[13]
I analog ground: 0 V reference. This should nominally be the same
voltage as V
SSIO
/V
SSCORE
, but should be isolated to minimize noise and
error.
V
DD(3V3)
15, 60,
71, 89,
112,
125,
146,
165,
181,
198
[13]
G3, P6,
P8, U13,
P17,
K16,
C17,
B13, C9,
D7
[13]
I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
n.c. 30, 117,
141
[13]
J4, L14,
G14
[13]
I not connected pins: These pins must be left unconnected (floating).
V
DD(DCDC)(3V3)
26, 86,
174
[13]
H4, P11,
D11
[13]
I 3.3 V DC-to-DC converter supply voltage: This is the power supply for
the on-chip DC-to-DC converter.
V
DDA
20
[13]
G4
[13]
I analog 3.3 V pad supply voltage: This should be nominally the same
voltage as V
DD(3V3)
but should be isolated to minimize noise and error.
This voltage is used to power the ADC and DAC.
Table 4. Pin description …continued
Symbol Pin Ball Type Description