Datasheet

LPC2478 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 16 October 2013 67 of 93
NXP Semiconductors
LPC2478
Single-chip 16-bit/32-bit microcontroller
[1] See Figure 18.
Table 17. Dynamic characteristics: Dynamic external memory interface
C
L
= 30 pF on all pins, T
amb
=  40  C to 85  C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.3 V, EMC Dynamic Read Config Register = 0x1
(RD = 01), T
cy(CCLK)
= 1/CCLK
Symbol Parameter Conditions Min Typ Max Unit
Common
t
d(SV)
chip select valid delay
time
[1]
- 3 + T
cy(CCLK)
1.5 + T
cy(CCLK)
ns
t
h(S)
chip select hold time
[1]
4 + T
cy(CCLK)
3 + T
cy(CCLK)
-ns
t
d(RASV)
row address strobe valid
delay time
[1]
- 3 + T
cy(CCLK)
1.5 + T
cy(CCLK)
ns
t
h(RAS)
row address strobe hold
time
[1]
3 + T
cy(CCLK)
2.3 + T
cy(CCLK)
-ns
t
d(CASV)
column address strobe
valid delay time
[1]
- 3.4 + T
cy(CCLK)
2.1 + T
cy(CCLK)
ns
t
h(CAS)
column address strobe
hold time
[1]
4 + T
cy(CCLK)
3 + T
cy(CCLK)
-ns
t
d(WV)
write valid delay time
[1]
- 3.4 + T
cy(CCLK)
2.1 + T
cy(CCLK)
ns
t
h(W)
write hold time
[1]
4 + T
cy(CCLK)
3 + T
cy(CCLK)
-ns
t
d(GV)
output enable valid delay
time
[1]
- 3 + T
cy(CCLK)
1.3 + T
cy(CCLK)
ns
t
h(G)
output enable hold time
[1]
4 + T
cy(CCLK)
2.1 + T
cy(CCLK)
-ns
t
d(AV)
address valid delay time
[1]
- 2.6 + T
cy(CCLK)
1.4 + T
cy(CCLK)
ns
t
h(A)
address hold time
[1]
4 + T
cy(CCLK)
2.3 + T
cy(CCLK)
-ns
Read cycle parameters
t
su(D)
data input set-up time
[1]
2.6 + T
cy(CCLK)
1.5 + T
cy(CCLK)
-ns
t
h(D)
data input hold time
[1]
2.6 + T
cy(CCLK)
1.3 + T
cy(CCLK)
-ns
Write cycle parameters
t
d(QV)
data output valid delay
time
[1]
- 2.6 + T
cy(CCLK)
/2 4.8 + T
cy(CCLK)
/2 ns
t
h(Q)
data output hold time
[1]
3.8 + T
cy(CCLK)
3.4 + T
cy(CCLK)
-ns