- NXP ARM Microcontroller Product Data Sheet
Table Of Contents
- 1. Introduction
- 2. General description
- 3. Features
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 8. Block description
- 9. Limiting values
- 10. Thermal characteristics
- 11. Static characteristics
- 12. Dynamic characteristics
- 13. Package outline
- 14. Soldering
- 15. Abbreviations
- 16. References
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
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LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 23 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
• Event detection is fully asynchronous, so no clock is required
8.3.4.2 Description
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
The vectored interrupt-controller inputs are active HIGH.
8.3.4.3 Event-router pin description and mapping to register bit positions
The event router module in the LPC2917/19 is connected to the pins listed below. The
pins are combined with other functions on the port pins of the LPC2917/19. Table 13
shows the pins connected to the event router, and also the corresponding bit position in
the event-router registers and the default polarity.
8.4 Peripheral subsystem
8.4.1 Peripheral subsystem clock description
The peripheral subsystem is clocked by a number of different clocks:
• CLK_SYS_PESS
• CLK_UART0/1
• CLK_SPI0/1/2
• CLK_TMR0/1/2/3
Table 13. Event-router pin connections
Symbol Direction Bit position Description Default
polarity
EXTINT0 in 0 external interrupt input 0 1
EXTINT1 in 1 external interrupt input 1 1
EXTINT2 in 2 external interrupt input 2 1
EXTINT3 in 3 external interrupt input 3 1
EXTINT4 in 4 external interrupt input 4 1
EXTINT5 in 5 external interrupt input 5 1
EXTINT6 in 6 external interrupt input 6 1
EXTINT7 in 7 external interrupt input 7 1
CAN0 RXD in 8 CAN0 receive data input wake-up 0
CAN1 RXD in 9 CAN1 receive data input wake-up 0
- - 13 - 10 reserved -
LIN0 RXD in 14 LIN0 receive data input wake-up 0
LIN1 RXD in 15 LIN1 receive data input wake-up 0
- - 21 - 16 reserved -
- na 22 CAN interrupt (internal) 1
- na 23 VIC FIQ (internal) 1
- na 24 VIC IRQ (internal) 1
- - 26 - 25 reserved -