- NXP ARM Microcontroller Product Data Sheet

ManualsBrandsNXP Semiconductors ManualsNetwork RouterLPC2919

Table Of Contents

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1. Introduction

1.1 About this document

This document lists detailed information about the LPC2917/19 device. It focuses on

factual information like pinning, characteristics etc. Short descriptions are used to outline

the concept of the features and functions. More details and background on developing

applications for this device are given in the LPC2917/19 User Manual (see Ref. 1

). No

explicit references are made to the User Manual.

1.2 Intended audience

This document is written for engineers evaluating and/or developing systems, hard-

and/or software for the LPC2917/19. Some basic knowledge of ARM processors and

architecture and ARM968E-S in particular is assumed (see Ref. 2

2. General description

2.1 Architectural overview

The LPC2917/19 consists of:

• An ARM968E-S processor with real-time emulation support

• An AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the

on-chip memory controllers

• Two DTL buses (a universal NXP interface) for interfacing to the interrupt controller

and the Power, Clock and Reset Control cluster (also called subsystem)

• Three VLSI Peripheral Buses (VPB - a compatible superset of ARM's AMBA

advanced peripheral bus) for connection to on-chip peripherals clustered in

subsystems.

The LPC2917/19 configures the ARM968E-S processor in little-endian byte order. All

peripherals run at their own clock frequency to optimize the total system power

consumption. The AHB2VPB bridge used in the subsystems contains a write-ahead buffer

one transaction deep. This implies that when the ARM968E-S issues a buffered write

action to a register located on the VPB side of the bridge, it continues even though the

actual write may not yet have taken place. Completion of a second write to the same

subsystem will not be executed until the first write is finished.

LPC2917/19

ARM9 microcontroller with CAN and LIN

Rev. 1.01 — 15 November 2007 Preliminary data sheet

Summary of content (68 pages)

PAGE 1
D D R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Preliminary data sheet D Rev. 1.01 — 15 November 2007 R R R ARM9 microcontroller with CAN and LIN D D D LPC2917/19 D FT FT A A R R D D D 1. Introduction R A FT This document is written for engineers evaluating and/or developing systems, hardand/or software for the LPC2917/19.
PAGE 2
D D D D D R R R R R FT FT FT FT FT LPC2917/19 D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The ARM968E-S is a general purpose 32-bit RISC processor, which offers high performance and very low power consumption.
PAGE 3
D D D D D R R R R R FT FT FT FT FT LPC2917/19 D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A FT FT A A R R D D In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one of 32 kB and one of 16 kB. Both may be used for code and/or data storage.
PAGE 4
D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D D FT FT A A R R D D D R A Type number Package Name Description Version LPC2917FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm, pin SOT486-1 pitch 0.
PAGE 5
D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5. Block diagram FT LPC2917/19 FT FT NXP Semiconductors D FT FT A A R R D D D R A DTCM 16 Kb D ARM968E-S FT ITCM 16 Kb LPC2917/19 R A Vectored Interrupt Controller (VIC) AH B2D TL Bridge s m IEEE 1149.
PAGE 6
D D D D D R R R R R FT FT FT FT FT LPC2917/19 D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 6.1 Pinning A FT FT A A R R D D D 6. Pinning information A A A A A NXP Semiconductors D D R D 109 FT R 144 A A 1 108 LPC2917FBD144 LPC2919FBD144 72 73 37 36 144PINS Fig 2. Pin configuration for SOT486-1 (LQFP144) 6.2 Pin description 6.2.
PAGE 7
D D D D D R R R R R D R R R A FT A R - PWM3 CAP2 EXTBUS D23 1.8 V power supply for digital core VSS(CORE) 19 ground for digital core P1.31 20 GPIO 1, pin 31 TIMER0 CAP1 TIMER0 MAT1 EXTINT5 VSS(IO) 21 ground for I/O P1.30 22 GPIO 1, pin 30 TIMER0 CAP0 TIMER0 MAT0 EXTINT4 P3.8 23 GPIO 3, pin 8 SPI2 SCS0 PWM1 MAT2 - P3.9 24 GPIO 3, pin 9 SPI2 SDO PWM1 MAT3 - P1.29 25 GPIO 1, pin 29 TIMER1 CAP0, EXT START PWM TRAP0 PWM3 MAT5 P1.
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D D D D D R R R R R D R R FT D F FT FT D FT FT A A R R D Function 3 A A A Function 2 R R R Function 1 R A D D Function 0 (default) D R FT FT A A R R D D D Description FT FT FT FT Pin A A A A R R D D D LQFP144 pin assignment …continued Symbol FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN Table 3. A A A A A NXP Semiconductors 3.3 V power supply for I/O P2.
PAGE 9
D D D D D R R R R R D R R R FT R FT D EXTBUS D24 A CAN0 TxD R - D GPIO 0, pin 0 FT Function 3 A Function 2 R Function 1 F D D Function 0 (default) A FT FT A A R R D D D Description D A FT FT A A R R R 93 D D D Pin FT FT FT FT P0.0 LQFP144 pin assignment …continued A A A A R R D D D Symbol FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN Table 3. A A A A A NXP Semiconductors R 94 ground for I/O P0.
PAGE 10
D D D D D R R R R R D R R R A FT R CAN1 TxD P3.5 135 GPIO 3, pin 5 TIMER3 MAT3 PWM2 MAT5 CAN1 RxD P2.18 136 GPIO 2, pin 18 - PWM1 CAP1 EXTBUS D16 P2.19 137 GPIO 2, pin 19 - PWM1 CAP2 EXTBUS D17 P0.20 138 GPIO 0, pin 20 ADC2 IN4 PWM2 MAT2 EXTBUS A16 P0.21 139 GPIO 0, pin 21 ADC2 IN5 PWM2 MAT3 EXTBUS A17 P0.22 140 GPIO 0, pin 22 ADC2 IN6 PWM2 MAT4 EXTBUS A18 VSS(IO) 141 ground for I/O P0.23 142 GPIO 0, pin 23 ADC2 IN7 PWM2 MAT5 EXTBUS A19 P2.
PAGE 11
D D D D D R R R R R FT FT FT FT FT LPC2917/19 D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can be used to connect a debugger probe for the embedded ARM processor.
PAGE 12
D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D R DTCM 16 Kb A ARM968E-S D D ITCM 16 Kb LPC2917/19 FT D R Vectored Interrupt Controller (VIC) AH B2D TL Bridge SYS_CLK A s m IEEE 1149.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The next table contains an overview of all the base blocks in the LPC2917/19 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D PWM 0 CLK_MSCSS_PWM1 PWM 0 CLK_MSCSS_PWM2 PWM 0 CLK_MSCSS_PWM3 PWM 0 D R R D A FT D D CLK_MSCSS_PWM0 R A FT D R A CLK_MSCSS_ADC1_V VPB side of ADC 1 PB CLK_MSCSS_ADC2_V VPB side of ADC 2 PB BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK BASE_CLK_TESTSHELL UART 0 interface clock CLK_UART1 UART 1 interface clock CLK_SPI0 SPI 0 interface clock CLK_SPI1 SPI 1 interface clock CLK_SPI2 SPI 2 interface clock CLK_TMR
PAGE 15
D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the boot loader.
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D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT Configuration-register access FT A A R R D Initialization A A A A R R D D D Both buffer lines are invalidated after: FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN D D Data-latch reading R A FT Index-sector reading D • • • • A A A A A NXP Semiconductors R A The modes of operation are listed in Table 8. Table 8.
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D D D D D R R R R R D R R R R A F A FT D A FT D R 0001 0000h D 64 R 8 R 0000 E000h D 8 D 7 FT 0000 C000h FT 0000 A000h 8 A 8 6 A 5 R 0000 8000h D 8 FT 4 A 0000 6000h FT R R 8 A D D 3 D R FT FT A A R R D D D Sector base address FT FT FT FT Sector size (kB) A A A A R R D D D Flash sector overview …continued Sector number FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN Table 9.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. D FT FT A A R R D D D 8.
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D D D D D R R R R R D R R FT 110 bank 6 111 bank 7 R FT FT A A R D D bank 5 R A FT D R A 8.2.3 External static-memory controller pin description The external static-memory controller module in the LPC2917/19 has the following pins, which are combined with other functions on the port pins of the LPC2917/19. Table 12 shows the external memory controller pins. Table 12.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D CLK(SYS) D D R A FT D R CS A OE_N ADDR DATA WSTOEN WST1 WSTOEN=3, WST1=7 Fig 4. Reading from external memory A timing diagram for writing to external memory is shown In Figure 5.
PAGE 21
D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Usage of the idle/turn-around time (IDCY) is demonstrated In Figure 6. Extra wait states are added between a read and a write cycle in the same external memory device.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT D D The general subsystem is clocked by CLK_SYS_GESS, see Section 7.2.2. FT A A R R D 8.3.1 General subsystem clock description A A A A R R D D D ARM9 microcontroller with CAN and LIN 8.3 General subsystem FT LPC2917/19 FT FT NXP Semiconductors R A FT 8.3.2 Chip and feature identification D R A 8.3.2.
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D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D A F FT FT A A R R R D FT The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT D Overview D 8.4.2.1 FT A A R R D 8.4.2 Watchdog timer A A A A R R D D D ARM9 microcontroller with CAN and LIN • CLK_SAFE see Section 7.2.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D timer has four capture inputs and/or match outputs. Connection to device pins depends on the configuration programmed into the port function-select registers.
PAGE 26
D D D D D R R R R R D R R FT TIMER x capture input 3 TIMERx MAT[0] OUT TIMER x match output 0 TIMERx MAT[1] OUT TIMER x match output 1 TIMERx MAT[2] OUT TIMER x match output 2 TIMERx MAT[3] OUT TIMER x match output 3 R FT FT A A R D R A FT D R A 8.4.3.4 D IN Timer clock description The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx (x = 0-3), see Section 7.2.2. Note that each timer has its own CLK_TMRx branch clock for power management.
PAGE 27
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The UART modules are clocked by two different clocks; CLK_SYS_PESS and CLK_UARTx (x = 0-1), see Section 7.2.2. Note that each UART has its own CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx clocks is identical since they are derived from the same base clock BASE_CLK_UART.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI.
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D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT The LPC2917/19 contains four general-purpose I/O ports located at different peripheral base addresses. In the 144-pin package all four ports are available. All I/O pins are bi-directional, and the direction can be programmed individually. The I/O pad behavior depends on the configuration programmed in the port function-select registers.
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D D D D D R R R R R FT FT FT FT FT LPC2917/19 D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D A F D FT FT A A R R D 8.5.1 Overview R FT FT A A R R D D D 8.5 CAN gateway A A A A A NXP Semiconductors D D Controller Area Network (CAN) is the definition of a high-performance communication protocol for serial data communication.
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D D D D D R R R R R D R R D A FT R R FT FT A A R D D R A FT D R Programmable inter-byte space A Hardware or software parity generation Automatic checksum generation Fault confinement Fractional baud-rate generator 8.6.2 LIN pin description The two LIN 2.0 master controllers in the LPC2917/19 have the pins listed below. The LIN pins are combined with other functions on the port pins of the LPC2917/19. Table 19 shows the LIN pins. For more information see Ref. 1 subsection 3.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D control. Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Each ADC module has four start inputs. An ADC conversion is started when one of the start ADC conditions is valid: D R R D FT FT A A • start 0: ADC external start input pin; can be triggered at a positive or negative edge.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R F D FT FT A A R R D ADC1_EXT_START A FT FT A A R R D D D ADC2_EXT_START FT LPC2917/19 FT FT NXP Semiconductors D D R A FT D R A pause_0 so0 pause MSCSS(1) TIMER 0 c0 m0 so1 c1 m1 so2 c2 m2 pause_0 c3 m3 ADC1(2) st0 st1 st2 so st3 MSCSS(1) TIMER 1 c0 m0 c1 m1 c2 m2 c3 m3 pause PW
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D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D CLK_MSCSS_MTMR0/1 clocks the timers A A A A R R D D D CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-VPB bus bridge CLK_MSCSS_VPB clocks the subsystem VPB bus FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN D CLK_MSCSS_PWM0..3 clocks the PWMs.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than or equal to the system clock frequency.
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D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_VPB and CLK_ADCx (x = 1 or 2), see Section 7.2.2. Note that each ADC has its own CLK_ADCx and CLK_MSCSS_ADCx_VPB branch clocks for power management. If an ADC is unused both its CLK_MSCSS_ADCx_VPB and CLK_ADCx can be switched off.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R F FT FT cycle and cycle period allows the PWM to control the amount of power to be transferred to the load.
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D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT MSCSS timer-pin description FT A A R R D 8.7.7.3 FT FT FT FT See section Section 8.4.3.2 for a description of the timers. A A A A R R D D D Description FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN 8.7.7.2 A A A A A NXP Semiconductors D D R MSCSS timer 0 has no external pins.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D xo 50 m _ou t FT FT FT FT A A A A R R D D D Power, Clock & Reset FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN xo5 0m _in A A A A A NXP Semiconductors D D R A FT CGU D PMU Xtal Oscillator R Low Power Ring Oscillator (Ringo) base clocks C lock E na ble C on trol FDIV[6:0] C lo ck Ga te s out0 out1 … out9 A PLL
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D Control PLL with power-down R A Very low-power ring oscillator, always on to provide a ’safe clock’ FT D Seven fractional clock dividers with L/D division R A Individual source selector for each base clock, with glitch-free switching Autonomous clock-activity detection on every clock source Protection against switching to invalid or inactive clock sources E
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Clock Source Bus FT LPC2917/19 FT FT NXP Semiconductors LP_OSC D D R A FT OUT 0 FDIV1 OUT 1 FDIV6 OUT 9 A FDIV0 R PLL D Xtal Oscilator Frequency Monitor Clock Detection DTL MMIO Interface Fig 12.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D OSC1M D D R A FDIV0..6 FT D R XO50M A PLL160M clkout / clkout120 / clkout240 Output Control Clock outputs Fig 13.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid, and values of ’CLK_SEL’ that would select those clocks are masked and not written to the control registers.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D D R A P23 FT D clkout R A Direct / MDIV MSEL Fig 14. PLL block diagram Triple output phases For applications that require multiple clock phases two additional clock outputs can be enabled by setting register P23EN to ’1’, thus giving three clocks with a 120° phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers.
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D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D A F FT FT A A R R R D FT The key features of the Reset Generation Unit (RGU) are: FT A A R R D Overview D D D 8.8.5 Reset Generation Unit (RGU) FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN 8.8.5.1 A A A A A NXP Semiconductors D D Reset controlled individually per subsystem A FT Automatic reset stretching and release D R A 8.8.
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D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D The RGU module in the LPC2917/19 has the following pins. Table 26 shows the RGU pins. FT A A R R D D D RGU pin description FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN 8.8.5.3 A A A A A NXP Semiconductors D RGU pins D R Table 26.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D D R A FT D RUN 0 0 1 CLK_SYS_CPU BASE_SYS_CLK + + 1 CLK_SYS BASE_SYS_CLK + + 1 CLK_SYS_PCR BASE_SYS_CLK + + 1 CLK_SYS_FMC BASE_SYS_CLK + + + CLK_SYS_RAM0 BASE_SYS_CLK + + + CLK_SYS_RAM1 BASE_SYS_CLK + + + CLK_SYS_SMC BASE_SYS_CLK + + + CLK_SYS_GESS BASE_SYS_CLK + + + CLK_SYS_VIC BASE_SYS_CLK + + + CLK_SYS_PESS BASE_SYS_CLK + + + CLK_SYS_GPIO0
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D D FT FT A A R R D D Table 27.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold.
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D D D D D R R R R R D R R FT −33 mA - +38 mA R A FT FT D D R A D R A Tstg Storage temperature. −40 +150 °C Tamb Ambient temperature. −40 +85 °C −40 +125 °C [6] Virtual junction temperature. Memory nendu(fl) Endurance of flash memory. - 100 000 cycle tret(fl) Flash memory retention time. - 20 year Electrostatic discharge Vesd Electrostatic discharge voltage. On all pins. Human body model. [7] −2000 +2000 V Machine model.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A D D Unit 1.71 1.80 1.89 V - 1.1 2.5 mA/ MHz - 30 450 μA 2.7 - 3.6 V Oscillator and PLL supply voltage. 1.71 1.80 1.89 V IDDD(OSC_PLL) Oscillator and PLL supply start-up current. Normal mode 1.5 - 3 mA - - 1 mA - - 2 μA 3.0 3.3 3.6 V Normal mode - - 1.
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D D D D D R R R R R D R R D A FT R R - - 1 μA All port pins, VI = 3.3 V; VI = 5.5 V. 25 50 100 μA All port pins, RESET_N, TRST_N, TDI, JTAGSEL, TMS: VI = 0 V; VI > 3.6 V is not allowed. −25 −50 −100 μA - 3 8 pF 0 - VDD(IO) V VDD(IO) – 0.4 - - V A Max Unit FT D D R A R A Output pins and I/O pins configured as output VO Output voltage. VOH HIGH-state output voltage. VOL LOW-state output voltage. IOL = 4 mA - - 0.4 V CL Load capacitance.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R Max Unit Cxtal = 10 pF; Cext = 18 pF - - 160 Ω Cxtal = 20 pF; Cext = 39 pF - - 60 Ω - - 80 Ω 2 pF FT D D R FT [5] Power-up reset Vtrip(high) High trip-level voltage. [6] 1.2 1.4 1.6 V Vtrip(low) Low trip-level voltage. [6] 1.1 1.3 1.5 V Difference between high and low trip-level voltages.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A Unit A R Max F D D Typ D D R - 80 MHz Tclk(sys) System clock period. See Table 23. 12.5 - 100 ns 0.36 0.4 0.42 MHz - 6 100 μs Maximum frequency is the clock input of an external clock source applied to the Xin pin. 10 - 80 MHz At maximum frequency. - 500 - μs 10 - 25 MHz D 10 R A Low-Power Ring Oscillator fref(RO) RO reference frequency. tstartup Start-up time.
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R Internal write-access time. - - 24.9 ns UART frequency. 1⁄ 65024fclk(uart) - 1⁄ f 2 clk(uart) MHz Master operation. 1⁄ 65024fclk(spi) - 1⁄ f 2 clk(spi) MHz Slave operation. 1⁄ 65024fclk(spi) - 1⁄ f 4 clk(spi) MHz [2] - 0.4 1 ns FT FT A Unit A R Max D D R A FT D R Jitter Specification CAN TXD pin Cycle-to-cycle jitter (peak-to-peak value).
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 13. Package outline FT LPC2917/19 FT FT NXP Semiconductors D FT A A R R D LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 14.1 Introduction A FT FT A A R R D D D 14. Soldering FT LPC2917/19 FT FT NXP Semiconductors D D R There is no soldering method that is ideal for all surface mount IC packages.
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D D D D D R R R R R D R R D A FT R A F FT FT A A R R D D D D 220 ≥ 2.5 220 220 D 235 R < 2.5 D ≥ 350 FT < 350 FT A A R R D Volume (mm3) R R FT FT A A R R D D D Package reflow temperature (°C) FT FT FT FT Package thickness (mm) A A A A R R D D D SnPb eutectic process (from J-STD-020C) FT FT FT FT FT LPC2917/19 ARM9 microcontroller with CAN and LIN Table 32. A A A A A NXP Semiconductors A FT D R A Table 33.
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D D D D D R R R R R A A A A A FT FT FT LPC2917/19 FT FT D R R FT FT FT FT ARM9 microcontroller with CAN and LIN A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D To overcome these problems the double-wave soldering method was specifically developed.
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D D D D D R R R R R D R R FT D suitable − DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[6] suitable − PLCC[7], SO, SOJ suitable R not suitable FT FT A A R BGA, LBGA, LFBGA, SQFP, SSOP..T[5], TFBGA, VFBGA, XSON F D D Dipping D D R A FT suitable − SSOP, TSSOP, VSO, VSSOP not recommended[9] suitable − CWQCCN..L[10], WQCCN..
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D D D D D R R R R R D R R FT D A FT Slot Control List BEL Buffer Entry List CCO Current Controlled Oscillator D SCU Function Select Port x,y (use without the P if there are no x,y) SCL R A VLSI Peripheral bus © NXP B.V. 2007. All rights reserved. Rev. 1.
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D D D D D R R R R R FT FT FT FT FT LPC2917/19 D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 16.
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D D D D D R R R R R D R R FT D A F FT FT A A R R R D D A FT Part LPC2915 removed D R A • • LPC2915_17_19_1 R Preliminary data sheet D Supersedes FT LPC2917_19_1.
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D D D D D R R R R R A A A A A FT FT D R R FT FT FT FT A A A A R R D D D ARM9 microcontroller with CAN and LIN D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 18.1 Data sheet status A FT FT A A R R D D D 18. Legal information FT LPC2917/19 FT FT NXP Semiconductors D D R Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development.
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D D D D D R R R R R D R R R A FT R A FT FT A D D R A D R A 67 of 68 FT 23 23 23 24 24 24 24 24 24 24 25 25 26 26 26 26 26 27 27 27 27 28 28 28 29 29 29 29 29 30 30 30 30 30 30 31 © NXP B.V. 2007. All rights reserved. Rev. 1.01 — 15 November 2007 R R 22 22 22 22 22 22 22 22 22 22 23 continued >> Preliminary data sheet F D D Chip and feature identification . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . .
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D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D F FT FT A A A D FT FT A A R R D D D R A D R A All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.