- NXP ARM Microcontroller Product Data Sheet
Table Of Contents
- 1. Introduction
- 2. General description
- 3. Features
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 8. Block description
- 9. Limiting values
- 10. Thermal characteristics
- 11. Static characteristics
- 12. Dynamic characteristics
- 13. Package outline
- 14. Soldering
- 15. Abbreviations
- 16. References
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
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LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 12 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
Fig 3. LPC2917/19 block diagram, overview of clock areas
General Subsystem
Event Router (ER)
System Control Unit (SCU)
Chip Feature ID (CFID)
AHB2VPB
Bridge
s
IEEE 1149.1 JTAG TEST and
DEBUG INTERFACE
LPC2917/19
DTCM
16 Kb
ITCM
16 Kb
ARM968E-S
m
s
s
s
s
s
s
s
s
s
External Static Memory
Controller (SMC)
Embedded
SRAM Memory 32 Kb
SRAM Controller #0
Embedded
FLASH Memory
512 - 768 Kb
FLASH Memory Controller (FMC)
Embedded
SRAM Memory 16 Kb
SRAM Controller #1
GLOBAL ACCEPTANCE
FILTER
2 Kbyte Static RAM
LIN MASTER 0/1
CAN Controller
0, 1
Vectored Interrupt
Controller (VIC)
AHB2VPB
Bridge
AHB2DTL
Bridge
Modulation and Sampling
Control Subsystem
PWM 0, 1, 2, 3
ADC 1, 2
Timer 0, 1 (MTMR)
AHB2VPB
Bridge
Power Clock Reset
Control Subsystem
Power Management Unit (PMU)
Reset Generation Unit (RGU)
Clock Generation Unit (CGU)
AHB2DTL
Bridge
Peripheral Subsystem
General Purpose IO (GPIO)
0, 1, 2, 3
Timer (TMR)
0, 1, 2, 3
Watchdog Timer (WDT)
UART 0, 1
AHB2VPB
Bridge
TMR_CLK
SAFE_CLK
UART_CLK
SPI_CLK
PCR_CLK
IVNSS_CLK
ADC_CLK
MSCSS_CLK
SYS_CLK
SPI 0, 1, 2
s