- NXP ARM Microcontroller Product Data Sheet
Table Of Contents
- 1. Introduction
- 2. General description
- 3. Features
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 8. Block description
- 9. Limiting values
- 10. Thermal characteristics
- 11. Static characteristics
- 12. Dynamic characteristics
- 13. Package outline
- 14. Soldering
- 15. Abbreviations
- 16. References
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
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LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 35 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
• CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-VPB bus bridge
• CLK_MSCSS_VPB clocks the subsystem VPB bus
• CLK_MSCSS_MTMR0/1 clocks the timers
• CLK_MSCSS_PWM0..3 clocks the PWMs.
Each ADC has two clock areas; a VPB part clocked by CLK_MSCSS_ADCx_VPB (x = 1
or 2) and a control part for the analog section clocked by CLK_ADCx = 1 or 2), see
Section 7.2.2
.
All clocks are derived from the BASE_MSCSS_CLK, except for CLK_SYS_MSCSS_A
which is derived form BASE_SYS_CLK, and the CLK_ADCx clocks which are derived
from BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding
clocks can be switched off.
8.7.5 Analog-to-digital converter
8.7.5.1 Overview
The MSCSS in the LPC2917/19 includes two 10-bit successive-approximation
analog-to-digital converters.
The key features of the ADC interface module are:
• ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to
3.3 V
• External reference-level inputs
• 400 ksamples per second at 10-bit resolution up to 1500 ksamples per second at 2-bit
resolution
• Programmable resolution from 2-bit to 10-bit
• Single analog-to-digital conversion scan mode and continuous analog-to-digital
conversion scan mode
• Optional conversion on transition on external start input, timer capture/match signal,
PWM_sync or ‘previous’ ADC
• Converted digital values are stored in a register for each channel
• Optional compare condition to generate a ‘less than’ or an ‘equal to or greater than’
compare-value indication for each channel
• Power-down mode
8.7.5.2 Description
The ADC block diagram, Figure 9
, shows the basic architecture of each ADC. The ADC
functionality is divided into two major parts; one part running on the MSCSS Subsystem
clock, the other on the ADC clock. This split into two clock domains affects the behavior
from a system-level perspective. The actual analog-to-digital conversions take place in the
ADC clock domain, but system control takes place in the system clock domain.
A mechanism is provided to modify configuration of the ADC and control the moment at
which the updated configuration is transferred to the ADC domain.