- NXP ARM Microcontroller Product Data Sheet
Table Of Contents
- 1. Introduction
- 2. General description
- 3. Features
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 8. Block description
- 9. Limiting values
- 10. Thermal characteristics
- 11. Static characteristics
- 12. Dynamic characteristics
- 13. Package outline
- 14. Soldering
- 15. Abbreviations
- 16. References
- 17. Revision history
- 18. Legal information
- 19. Contact information
- 20. Contents
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LPC2917_19_1 © NXP B.V. 2007. All rights reserved.
Preliminary data sheet Rev. 1.01 — 15 November 2007 50 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
8.8.6.3 PMU pin description
The PMU has no external pins.
8.9 Vectored interrupt controller
8.9.1 Overview
The LPC2917/19 contains a very flexible and powerful Vectored Interrupt Controller (VIC)
to interrupt the ARM processor on request.
The key features are:
• Level-active interrupt request with programmable polarity
• 56 interrupt-request inputs
• Software-interrupt request capability associated with each request input
• Observability of interrupt-request state before masking
• Software-programmable priority assignments to interrupt requests up to 15 levels
• Software-programmable routing of interrupt requests towards the ARM-processor
inputs IRQ and FIQ
• Fast identification of interrupt requests through vector
• Support for nesting of interrupt service routines
8.9.2 Description
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
• Target 0 is ARM processor FIQ (fast interrupt service)
• Target 1 is ARM processor IRQ (standard interrupt service)
CLK_SPI0 BASE_SPI_CLK + + +
CLK_SPI1 BASE_SPI_CLK + + +
CLK_SPI2 BASE_SPI_CLK + + +
CLK_TMR0 BASE_TMR_CLK + + +
CLK_TMR1 BASE_TMR_CLK + + +
CLK_TMR2 BASE_TMR_CLK + + +
CLK_TMR3 BASE_TMR_CLK + + +
CLK_ADC1 BASE_ADC_CLK + + +
CLK_ADC2 BASE_ADC_CLK + + +
CLK_TESTSHELL_IP BASE_CLK_TESTSHELL 0 0 1
Table 27. Branch clock overview
…continued
Legend:
"1" Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
"0" Indicates that the related register bit is tied off to logic LOW, all writes are ignored
“+” Indicates that the related register bit is readable and writable
Branch Clock Name Base Clock Implemented Switch On/Off
Mechanism
WAKEUP AUTO RUN