Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 180 (12x12) 16/32-Bit 270 MHz I/O number 20

1. General description

The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB

2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four

channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted

at consumer, industrial, medical, and communication markets. To optimize system power

consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock

Generation Unit (CGU) that provides dynamic clock gating and scaling.

2. Features and benefits

2.1 Key features

 CPU platform

 270 MHz, 32-bit ARM926EJ-S

 16 kB D-cache and 16 kB I-cache

 Memory Management Unit (MMU)

 Internal memory

 192 kB embedded SRAM

 External memory interface

 NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only)

 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM

 Security

 AES decryption engine (LPC3143 only)

 Secure one-time programmable memory for AES key storage and customer use

 128 bit unique ID per device for DRM schemes

 Communication and connectivity

 High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY

 Two I

S interfaces

 Integrated master/slave SPI

 Two master/slave I

C-bus interfaces

 Fast UART

 Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA

 Four-channel 10-bit ADC

 Integrated 4/8/16-bit 6800/8080 compatible LCD interface

 System functions

 Dynamic clock gating and scaling

 Multiple power domains

LPC3141/3143

Low-cost, low-power ARM926EJ microcontrollers with USB

High-speed OTG, SD/MMC, and NAND flash controller

Rev. 1 — 4 June 2012 Product data sheet

Summary of content (69 pages)

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LPC3141/3143 Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller Rev. 1 — 4 June 2012 Product data sheet 1. General description The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers  Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB  On the LPC3143 only: secure booting using an AES decryption engine from SPI flash, NAND flash, SD/MMC cards, UART, or USB.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 4. Block diagram JTAG interface LPC3141/3143 ARM926EJ-S INSTRUCTION CACHE 16 kB DATA CACHE 16 kB TEST/DEBUG INTERFACE master master DMA CONTROLLER USB 2.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 5. Pinning information 5.1 Pinning ball A1 index area LPC3141/3143 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aae082 Transparent top view Fig 2. Table 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row P 1 USB_VDDA33 2 USB_DP 3 mLCD_DB_14 4 mLCD_DB_13 5 mLCD_DB_7 6 mLCD_DB_3 7 mLCD_DB_5 8 mLCD_RS 9 mLCD_DB_1 10 TMS 11 I2SRX_WS0 12 UART_RXD 13 TRST_N 14 mUART_RTS_N - - - - Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin Cell type Description [3] state after reset[2] USB_DM N2 SUP3 AIO - AIO1 USB D connection with integrated 45  termination resistor. USB_VDDA12_PLL L1 SUP1 Supply - PS3 USB PLL supply.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin Cell type Description [3] state after reset[2] Serial Peripheral Interface (SPI) SPI_CS_OUT0[4] A7 SUP3 DO O DIO4 SPI chip select output (master).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] VSSE_IOC Pin Cell type Description [3] state after reset[2] B12; D6; D8; D9; G11; L9; L13 - Ground - PG1 - mLCD_CSB[4] K8 SUP8 DO O DIO4 LCD chip select (active LOW).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin Cell type Description [3] state after reset[2] I2S/digital audio output mI2STX_DATA0[4] M13 SUP3 DO/GPIO O DIO1 I2S serial data transmit output. mI2STX_BCK0[4] M12 SUP3 DO/GPIO O DIO1 I2S bit clock.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Digital Application Ball I/O function level [1] Pin Cell type Description [3] state after reset[2] EBI_D_5[4] D1 SUP4 DIO I DIO4 EBI data I/O 5. EBI_D_6[4] D2 SUP4 DIO I DIO4 EBI data I/O 6. EBI_D_7[4] C1 SUP4 DIO I DIO4 EBI data I/O 7.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 5. Supply domains Supply domain Voltage range Related supply pins SUP1 1.0 V to 1.3 V VDDI, VDDA12, USB_VDDA12_PLL, Digital core supply VPP (OTP read) SUP3 2.7 V to 3.6 V VDDE_IOC, ADC10B_VDDA33, Peripheral supply USB_VDDA33_DRV, USB_VDDA33, VPP (during OTP write) SUP4 1.65 V to 1.95 V (in 1.8 V mode) 2.5 V to 3.6 V (in 3.3 V mode) VDDE_IOA Peripheral supply for NAND flash interface SUP5 4.5 V to 5.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 6. Functional description 6.1 ARM926EJ-S The processor embedded in the chip is the ARM926EJ-S. It is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 6.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers • ARM926 debug access • Boundary scan • The ARM926 debug access can be permanently disabled through JTAG security bits in the One-Time Programmable memory (OTP) block. 6.4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices. Figure 4 shows a block diagram of the NAND flash controller module.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers • • • • • • Support for 8-bit and 16-bit flash devices. Support for any page size from 0.5 kB upwards. Programmable NAND flash timing parameters. Support for up to 4 NAND devices. Hardware AES decryption (LPC3143 only). Error Correction Module (ECC) for MLC NAND flash support: – Reed-Solomon error correction encoding and decoding.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers – output enable and write enable delays – extended wait • One chip select for synchronous memory and two chip selects for static memory devices. • • • • • • Power-saving modes. Dynamic memory self-refresh mode supported. Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts. Support for all AHB burst types. Little and big endian support.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers The LPC3141 ROM memory has the following features: • Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and USB (DFU class) interfaces. • Supports option to perform CRC32 checking on the boot image. • Contains pre-defined MMU table (16 kB) for simple systems. • Supports booting from managed NAND devices such as movi-NAND, iNAND, eMMC-NAND and eSD-NAND using SD/MMC boot mode.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers • Implemented as two independent 96 kB memory banks 6.9 Memory Card Interface (MCI) The MCI controller interface can be used to access memory cards according to the Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers • Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. • Contains UTMI+ compliant transceiver (PHY). • Supports interrupts. • This module has its own, integrated DMA engine. 6.11 DMA controller The DMA controller can perform DMA transfers on the AHB without using the CPU.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 9: Peripherals that support DMA …continued Peripheral name Supported transfer types I2S0/1 receive Peripheral to Memory I2S0/1 transmit Memory to peripheral PCM interface Memory to peripheral and peripheral to memory [1] AES decryption engine is available on LPC3143 only. 6.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Multiple masters can have access to different slaves at the same time. Figure 5 gives an overview of the multi-layer AHB configuration in the LPC3141/3143. AHB masters and slaves are numbered according to their AHB port number. LPC3141_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 June 2012 © NXP B.V. 2012. All rights reserved.
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LPC3141/3143 NXP Semiconductors master 0 ARM 926EJ-S 1 D-CACHE DMA I-CACHE Low-cost, low-power ARM926EJ microcontrollers USB-OTG AHB MASTER 2 3 slave 0 AHB-APB BRIDGE 0 0 1 EVENT ROUTER 1 AHB-APB BRIDGE 1 0 1 TIMER 0 2 AHB-APB BRIDGE 2 3 AHB-APB BRIDGE 3 4 AHB-APB BRIDGE 4 0 1 LCD 0 6 7 6 OTP 3 TIMER 3 5 4 IOCONFIG CGU 4 5 6 PWM I2C0 I2C1 3 UART SPI I2S0/1 0 DMA REGISTERS 5 SYSTEM CONTROL RNG TIMER 2 2 3 WDT 2 TIMER 1 PCM 2 10-bit ADC 1 NAND REGIST
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers This module has the following features: • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). • Round-Robin priority mechanism for bus arbitration: all masters have the same priority and get bus access in their natural order.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 6.15 Clock Generation Unit (CGU) The clock generation unit generates all clock signals in the system and controls the reset signals for all modules. The structure of the CGU is shown in Figure 6. Each output clock generated by the CGU belongs to one of the domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers – Each base clock can be programmed to have any one of the clock sources as an input clock. – Fractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. – Fractional dividers support clock stretching to obtain a (near) 50% duty cycle output clock. • Register interface to reset all modules under software control. • Based on the input of the Watchdog timer (see also Section 6.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers • After a reset, a register will indicate whether a reset has occurred because of a watchdog generated reset. • Watchdog timer can also be used as a normal timer in addition to the watchdog functionality (output m0). m0 EVENT ROUTER m1 CGU WDT APB INTERRUPT CONTROLLER FIQ IRQ reset 002aae086 Fig 7. Block diagram of the Watchdog Timer 6.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake-up the system from suspend mode (with all clocks deactivated).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 6.20 Random number generator The Random Number Generator (RNG) generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • True random number generator. • The random number register does not rely on any kind of reset.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers The SPI/SSI-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transfers. This module has the following features: • Supports Motorola SPI frame format with a word size of 8/16 bits. • Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size of 4 bit to 16 bit. • • • • • • • • Receive FIFO and transmit FIFO of 64 half-words each.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers – MP PCM: Multi-Protocol PCM. Configurable directional per slot. – IOM-2: Extended ISDN-Oriented modular. Double clocking physical format. • • • • Twelve 8-bit slots in a frame with enabling control per slot. Internal frame clock generation in master mode. Receive and transmit DMA handshaking using a request/clear protocol. Interrupt generation per frame.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers • Fast mode (400 kHz SCLwith 24 MHz APB clock; 325 kHz with12 MHz APB clock; 175 kHz with 6 MHz APB clock). • Interrupt support. • Supports DMA transfers (single). • Four modes of operation: – Master transmitter – Master receiver – Slave transmitter – Slave receiver 6.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 10. Pin descriptions of multiplexed pins …continued Pin Name Default Signal Alternate Signal Description mLCD_DB_3 LCD_DB_3 EBI_A_3 LCD_DB_3 — LCD bidirectional data line 3. EBI_A_3 — EBI address line 3. mLCD_DB_4 LCD_DB_4 EBI_A_4 LCD_DB_4 — LCD bidirectional data line 4. EBI_A_4 — EBI address line 4. mLCD_DB_5 LCD_DB_5 EBI_A_5 LCD_DB_5 — LCD bidirectional data line 5. EBI_A_5 — EBI address line 5.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 10. Pin descriptions of multiplexed pins …continued Pin Name Default Signal Alternate Signal Description NAND related pin multiplexing mNAND_RYBN0 NAND_RYBN0 MCI_DAT_4 NAND_RYBN0 — NAND flash controller Read/Not busy signal 0. MCI_DAT_4 — MCI card data input/output line 4. mNAND_RYBN1 NAND_RYBN1 MCI_DAT_5 NAND_RYBN1 — NAND flash controller Read/Not busy signal 1. MCI_DAT_5 — MCI card data input/output line 5.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers LPC31xx control NAND_NCS_[0:3] NAND_RYBN[0:3] EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE control NAND FLASH INTERFACE control (ALE, CLE) 2 2 address EBI_A_[1:0] 2 data 16 data 16 data control 3 16 EBI_A_0_ALE EBI_A_1_CLE EBI_D_[15:0] EBI SUP4 MPMC address EBI_A_[15:2] 14 address 16 1 control 6 data LCD_DB_[15:2] 14 LCD_DB_[15:2] (LCD mode)/ EBI_A_[15:2] (MPMC mode) 14 0 SYSCREG_MUX_LCD_EBI_SEL reg
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage (SUP4) can be different from the LCD supply voltage (SUP8). 6.29 Timer module The LPC3141/3143 contains four fully independent timer modules, which can be used to generate interrupts after a pre-set time interval has elapsed. This module has the following features: • Each timer is a 32 bit wide down-counter with selectable pre-scale.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 6.32.1 I2S AHB interface The I2S AHB interface has the following features: • • • • • Supports DMA transfers. Transmit FIFO (I2S transmit) or receive FIFO (I2S receive) of 4 stereo samples. Supports single 16 bit transfers to/from the left or right FIFO. Supports single 24 bit transfers to/from the left or right FIFO.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Typ Max Unit All digital I/O pins Vi input voltage 0.5 - +3.6 V Vo output voltage 0.5 - +3.6 V Io output current - 4 - mA VDDE_IOC = 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 8. Static characteristics Table 12: Static characteristics Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit input/output supply voltage NAND flash controller pads (SUP4) and LCD interface (SUP8); 1.8 V mode 1.65 1.8 1.95 V NAND flash controller pads (SUP4) and LCD interface (SUP8); 3.3 V mode 2.5 3.3 3.6 V other peripherals (SUP 3) 2.7 3.3 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 12: Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit [1] Ilatch I/O latch-up current (1.5VDD(IO)) < VI < (1.5VDD(IO)) - - 100 mA Ipu pull-up current inputs with pull-up; VI = 0; SUP4; SUP8; 1.8 V mode [1] 47 65 103 A SUP4; SUP8; 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 12: Static characteristics …continued Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IOZ OFF-state output current VO = 0 V; VO = VDD; no pull-up/down - - 7.25 A VIH HIGH-level input voltage [1] 0.7VDDE_IOC - - V VIL LOW-level input voltage [1] - - 0.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 13. ADC static characteristics VDD(ADC) = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified. Symbol Parameter VIA analog input voltage Nres(ADC) ADC resolution ED differential linearity error EL(adj) integral non-linearity Verr(O) offset error voltage Conditions Min [1] [1] On pin ADC10B_GNDA. [2] Conditions: VSSA = 0 V on pin ADC10B_GNDA, VDD(ADC) = 3.3 V.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD(ADC) - VSSA 1024 002aae752 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 8.1 Power consumption Table 14. Symbol Power consumption Parameter Standby power IDD P Conditions Min Typ Max Unit core; VDDI = 1.2 V - 1.1 - mA all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V - 0.175 - mA VDDE_IOA = 1.8 V - 0.001 - mA VDDE_IOB = 1.8 V - 0.0008 - mA VDDE_IOC = 3.3 v - 0.065 - mA ADC10B_VDDA33 = 3.3 V - 0 - mA USB_VDDA33 = 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 14. Symbol Power consumption …continued Parameter Conditions Min Typ Max Unit External SDRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; without dynamic clock scaling[4] IDD P Supply current Power dissipation core; VDDI = 1.2 V - 36.1 - mA all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V - 1.61 - mA VDDE_IOA = 1.8 V - 3.79 - mA VDDE_IOB = 1.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 14. Symbol Power consumption …continued Parameter Conditions Min Typ Max Unit Internal SRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; without dynamic clock scaling; MMU off[6] IDD Supply current P Power dissipation core; VDDI = 1.2 V - 37.95 - mA all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V - 2.1 - mA VDDE_IOA = 1.8 V - 2.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9. Dynamic characteristics 9.1 LCD controller 9.1.1 Intel 8080 mode Table 15. Dynamic characteristics: LCD controller in Intel 8080 mode CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9.1.2 Motorola 6800 mode Table 16. Dynamic characteristics: LCD controller in Motorola 6800 mode CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9.1.3 Serial mode Table 17. Dynamic characteristics: LCD controller serial mode CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9.2 SRAM controller Table 18. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8). Symbol Parameter Conditions Min Typ Max Unit 1.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers [4] One HCLK cycle delay added when SYSCREG_MPMC_WAITREAD_DELAYx register bit 5 = 1. [5] WAITRD must  to WAITOEN for there to be any delay between CS active and BLS active. The maximum delay is limited to (WAITRD * HCLK). [6] There is one less HCLK cycle when SYSCREG_MPMC_WAITREAD_DELAYx bit 5 = 1. [7] The MPMC will ensure a minimum of one HCLK for this parameter. [8] This formula applies when WAITWR is  WAITWEN.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers EBI_NSTCS_X tCSLAV EBI_A_[15:0] tBLSHANV tCSLDV tWEHANV EBI_D_[15:0] tWELWEH tCSLWEL tWEHDNV tWELDV tBLSHDNV EBI_NWE tBLSLBLSH tCSLBLSL EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 002aae162 Fig 15. External memory write access to static memory LPC3141_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 June 2012 © NXP B.V. 2012. All rights reserved.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9.3 SDRAM controller Table 19. Dynamic characteristics of SDR SDRAM memory interface Tamb = 40 C to +85 C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8).[1][2][3] Symbol Parameter Conditions [4] Min Typical Max Unit - 80 90 MHz foper operating frequency tCLCX clock LOW time - 5.55 - ns tCHCX clock HIGH time - 5.55 - ns - - 3.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers TCLCL tCLCX tCHCX EBI_CLKOUT td(o) EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS th(o) READ NOP NOP NOP td(o) READ NOP NOP th(o) EBI_DQMx th(A) EBI_A_[15:2] BANK, COLUMN tsu(D) th(D) EBI_D_[15:0] DATA n CAS LATENCY = 2 DATA n+2 DATA n+1 DATA n+3 002aae121 EBI_CKE is HIGH. Fig 16.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9.4 NAND flash memory controller Table 20. Dynamic characteristics of the NAND Flash memory controller Tamb = 40 C to +85 C, unless otherwise specified.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 9.5 Crystal oscillator Table 21: Dynamic characteristics: crystal oscillator Symbol Parameter fosc Conditions Min Typ Max Unit oscillator frequency 10 12 25 MHz clk clock duty cycle 45 50 55 % Cxtal crystal capacitance input; on pin FFAST_IN - - 2 pF output; on pin FFAST_OUT - - 0.74 pF tstartup start-up time - 500 - s Pdrive drive power 100 - 500 µW 9.6 SPI Table 22.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIOH tSPIQV DATA VALID MOSI DATA VALID tSPIDSU MISO DATA VALID tSPIDH DATA VALID 002aad987 Fig 20. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tSPIOH tSPIQV MISO DATA VALID DATA VALID 002aad988 Fig 21.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIDH DATA VALID tSPIQV MISO tSPIOH DATA VALID DATA VALID 002aad989 Fig 22. SPI slave timing (CPHA = 0) 9.6.1 Texas Instruments synchronous serial mode (SSI mode) Table 23. Dynamic characteristic: SPI interface (SSI mode) Tamb = 40 C to +85 C; VDD(IO) (SUP3) over specified ranges.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers shifting edges SCK sampling edges MOSI MISO tsu(SPI_MISO) 002aad326 Fig 23. MISO line set-up time in SSI Master mode 9.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors LPC3141_43 Product data sheet 10. Application information Table 25.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 11. Marking Table 26. LPC3141_43 Product data sheet LPC3141/3143 Marking Line Marking Description A LPC3141/3143 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 June 2012 © NXP B.V. 2012. All rights reserved.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 12.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 13. Abbreviations Table 27.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Table 27.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 14. Revision history Table 28: Revision history Document ID Release date Data sheet status Change notice Supersedes LPC3141_43 v.1 20120604 Product data sheet - - LPC3141_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 June 2012 © NXP B.V. 2012. All rights reserved.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
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LPC3141/3143 NXP Semiconductors Low-cost, low-power ARM926EJ microcontrollers 17. Contents 1 2 2.1 3 3.1 4 5 5.1 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.28.1 6.28.2 6.28.3 6.29 6.30 6.31 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . .