Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 11 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
[1] Digital IO levels are explained in Tab le 5.
[2] I = input; I:PU = input with internal weak pull-up; I:PD = input with internal weak pull-down; O = output.
[3] Cell types are explained in Table 6
.
[4] Pin can be configured as GPIO pin in the IOCONFIG block.
[5] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can be selected to be used for alternative functions: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2).
[6] The polyfuses get unintentionally burned at random if VPP is powered to 2.3 V or greater before the VDDI is powered up to minimum
nominal voltage. This will destroy the sample because randomly blowing security fuses will lock the sample and also can corrupt the
AES key. For this reason it is recommended that VPP be powered by SUP1 at power on.
[7] To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see
UM10362 JTAG chapter for details.
EBI_D_5
[4]
D1 SUP4 DIO I DIO4 EBI data I/O 5.
EBI_D_6
[4]
D2 SUP4 DIO I DIO4 EBI data I/O 6.
EBI_D_7
[4]
C1 SUP4 DIO I DIO4 EBI data I/O 7.
EBI_D_8
[4]
B1 SUP4 DIO I DIO4 EBI data I/O 8.
EBI_D_9
[4]
A3 SUP4 DIO I DIO4 EBI data I/O 9.
EBI_D_10
[4]
A1 SUP4 DIO I DIO4 EBI data I/O 10.
EBI_D_11
[4]
C2 SUP4 DIO I DIO4 EBI data I/O 11.
EBI_D_12
[4]
G3 SUP4 DIO I DIO4 EBI data I/O 12.
EBI_D_13
[4]
D3 SUP4 DIO I DIO4 EBI data I/O 13.
EBI_D_14
[4]
E3 SUP4 DIO I DIO4 EBI data I/O 14.
EBI_D_15
[4]
F3 SUP4 DIO I DIO4 EBI data I/O 15.
EBI_DQM_0_NOE
[4]
H1 SUP4 DO O DIO4 NAND read enable (active LOW).
EBI_NWE
[4]
J2 SUP4 DO O DIO4 NAND write enable (active LOW).
NAND_NCS_0
[4]
J1 SUP4 DO O DIO4 NAND chip enable 0.
NAND_NCS_1
[4]
J3 SUP4 DO O DIO4 NAND chip enable 1.
NAND_NCS_2
[4]
K1 SUP4 DO O DIO4 NAND chip enable 2.
NAND_NCS_3
[4]
K2 SUP4 DO O DIO4 NAND chip enable 3.
mNAND_RYBN0
[4]
E6 SUP4 DI I DIO4 NAND ready/busy 0.
mNAND_RYBN1
[4]
E7 SUP4 DI I DIO4 NAND ready/busy 1.
mNAND_RYBN2
[4]
B4 SUP4 DI I DIO4 NAND ready/busy 2.
mNAND_RYBN3
[4]
D4 SUP4 DI I DIO4 NAND ready/busy 3.
EBI_NCAS_BLOUT_0
[4]
G1 SUP4 DO O DIO4 EBI lower lane byte select (7:0).
EBI_NRAS_BLOUT_1
[4]
H2 SUP4 DO O DIO4 EBI upper lane byte select (15:8).
Secure one-time programmable memory
VPP
[6]
A9;
C9
SUP1/
SUP3
Supply - PS3 Supply for polyfuse programming.
Pulse Width Modulation (PWM)
PWM_DATA
[4]
B9 SUP3 DO/GPIO O DIO1 PWM output.
Table 4. Pin description …continued
Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
Pin name BGA
Ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description