Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 13 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
6. Functional description
6.1 ARM926EJ-S
The processor embedded in the chip is the ARM926EJ-S. It is a member of the ARM9
family of general-purpose microprocessors. The ARM926EJ-S is intended for
multi-tasking applications where full memory management, high performance, and low
power are important.
This module has the following features:
• ARM926EJ-S processor core which uses a five-stage pipeline consisting of fetch,
decode, execute, memory and write stages. The processor supports both the 32-bit
ARM and 16-bit Thumb instruction sets, which allows a trade off between high
performance and high code density. The ARM926EJ-S also executes an extended
ARMv5TE instruction set which includes support for Java byte code execution.
• Contains an AMBA BIU for both data accesses and instruction fetches.
• Memory Management Unit (MMU).
• 16 kB instruction and 16 kB data separate cache memories with an 8 word line length.
The caches are organized using Harvard architecture.
• Little endian is supported.
• The ARM926EJ-S processor supports the ARM debug architecture and includes logic
to assist in both hardware and software debugging.
• Supports dynamic clock gating for power reduction.
• The processor core clock can be set equal to the AHB bus clock or to an integer
number times the AHB bus clock. The processor can be switched dynamically
between these settings.
• ARM stall support.