Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 14 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
6.2 Memory map
6.3 JTAG
The Joint Test Action Group (JTAG) interface allows the incorporation of the
LPC3141/3143 in a JTAG scan chain.
This module has the following features:
(1) LPC3143 only.
Fig 3. LPC3141/3143 memory map
0x0000 0000
0x0000 1000
0 GB
2 GB
4 GB
0x1102 8000
0x1104 0000
0x1105 8000
0x1200 0000
0x1202 0000
0x1300 0000
0x1300 8000
0x1300 B000
0x1500 0000
0x1600 0000
reserved
96 kB ISRAM0
96 kB ISRAM1
128 kB ISROM
reserved
reserved
reserved
reserved
external SRAM bank 0
external SRAM bank 1
external SDRAM bank 0
reserved
reserved
APB0 domain
APB1 domain
APB2 domain
APB3 domain
0x1700 0000
0x1700 8000
0x1700 9000
0x1800 0000
0x1800 0900
0x1900 0000
0x1900 1000
0x2000 0000
0x2002 0000
0x2004 0000
0x3000 0000
0x4000 0000
0x6000 0000
0x6000 1000
0x7000 0000
0x7000 0800
0x8000 0000
0xFFFF FFFF
reserved
MCI/SD/SDIO
USB OTG
APB4 domain
MPMC configuration registers
shadow area
LPC3141/3143
interrupt controller
NAND flash/AES buffer
(1)
reserved
reserved
0x1300 2000
0x1300 2400
0x1300 0000
event router
ADC10B
0x1300 2800
0x1300 3000
0x1300 4000
0x1300 6000
0x1300 5000
SysCReg
IOCONFIG
CGU
OTP
RNG
APB0 domain
0x1500 0400
0x1500 0000
PCM
reserved
LCD
0x1500 0800
0x1500 1000
0x1500 2000
0x1600 0000
0x1500 3000
reserved
UART
SPI
APB2 domain
0x1700 0800
0x1700 0000
DMA
NAND flash controller
0x1700 1000
0x1700 8000
reserved
APB4 domain
reserved
0x1600 0080
APB3 domain
0x1300 8400
0x1300 8000
timer 0
timer 1
0x1300 8800
0x1300 8C00
0x1300 9000
0x1300 A400
0x1300 B000
0x1300 A000
timer 2
timer 3
PWM
I
2
C0
I
2
C1
APB1 domain
reserved
002aae307
I
2
S system config
0x1600 0100
I2STX_0
0x1600 0180
I2STX_1
0x1600 0200
I2SRX_0
0x1600 0280
I2SRX_1
WDT