Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 15 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
• ARM926 debug access
• Boundary scan
• The ARM926 debug access can be permanently disabled through JTAG security bits
in the One-Time Programmable memory (OTP) block.
6.4 NAND flash controller
The NAND flash controller is used as a dedicated interface to NAND flash devices.
Figure 4
shows a block diagram of the NAND flash controller module. The heart of the
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An Error
Correction Code (ECC) module allows for hardware error correction for support of
Multi-Level Cell (MLC) NAND flash devices. The NAND flash controller is connected to
the AES block to support secure (encrypted) code execution (see Section 6.21
).
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects errors, and/or the AES decryption module can
decrypt data.
This module has the following features:
• Dedicated NAND flash interface with hardware controlled read and write accesses.
• Wear leveling support with 516-byte mode.
• Software controlled command and address transfers to support wide range of flash
devices.
• Software control mode where the ARM is directly master of the flash device.
(1) AES decoder available on LPC3143 only.
Fig 4. Block diagram of the NAND flash controller
002aae083
AHB MULTI-LAYER MATRIX
BUFFER
CONTROLLER
AES
DECODER
(1)
ECC
ENCODER/
DECODER
NAND INTERFACE
DMA transfer request