Datasheet
LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 16 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
• Support for 8-bit and 16-bit flash devices.
• Support for any page size from 0.5 kB upwards.
• Programmable NAND flash timing parameters.
• Support for up to 4 NAND devices.
• Hardware AES decryption (LPC3143 only).
• Error Correction Module (ECC) for MLC NAND flash support:
– Reed-Solomon error correction encoding and decoding.
– Uses Reed-Solomon code words with 9-bit symbols over GF(2
9
), a total codeword
length of 469 symbols, including 10 parity symbols, giving a minimum Hamming
distance of 11.
– Up to 8 symbol errors can be corrected per codeword.
– Error correction can be turned on and off to match the demands of the application.
– Parity generator for error correction encoding.
– Wear leveling information can be integrated into protected data.
– Interrupts generated after completion of error correction task with three interrupt
registers.
– Error correction statistics distributed to ARM using interrupt scheme.
– Interface is compatible with the ARM External Bus Interface (EBI).
6.5 Multi-Port Memory Controller (MPMC)
The multi-port memory controller supports the interface to different memory types, for
example:
• SDRAM
• Low-power SDRAM
• Static memory interface
This module has the following features:
• Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM.
• Address line supporting up to 128 MB (two 64Mx8 devices connected to a single chip
select) of dynamic memory.
• The MPMC has two AHB interfaces:
a. an interface for accessing external memory.
b. a separate control interface to program the MPMC. This enables the MPMC
registers to be situated in memory with other system peripheral registers.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance, particularly for
un-cached processors.
• Static memory features include:
– asynchronous page mode read
– programmable wait states
– bus turnaround delay