Datasheet
LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 18 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
The LPC3141 ROM memory has the following features:
• Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and
USB (DFU class) interfaces.
• Supports option to perform CRC32 checking on the boot image.
• Contains pre-defined MMU table (16 kB) for simple systems.
• Supports booting from managed NAND devices such as movi-NAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode.
The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and
GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be LOW during power-on reset (see UM10362 JTAG
chapter for details). Table 8
shows the various boot modes supported on the
LPC3141/3143:
[1] For security reasons this mode is disabled when JTAG security feature is used.
6.8 Internal RAM memory
The ISRAM (Internal Static RAM Memory) controller module is used as controller between
the AHB bus and the internal RAM memory. The internal RAM memory can be used as
working memory for the ARM processor and as temporary storage to execute the code
that is loaded by boot ROM from external devices such as SPI flash, NAND flash, and
SD/MMC cards.
This module has the following features:
• Capacity of 192 kB
Table 8. LPC3141/3143 boot modes
Boot mode GPIO0 GPIO1 GPIO2 Description
NAND 0 0 0 Boots from NAND flash. If proper image is not found,
boot ROM will switch to DFU boot mode.
SPI 0 0 1 Boot from SPI NOR flash connected to SPI_CS_OUT0. If
proper image is not found, boot ROM will switch to DFU
boot mode.
DFU 0 1 0 Device boots via USB using DFU class specification.
SD/MMC 0 1 1 Boot ROM searches all the partitions on the
SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.
If partition table is missing, it will start searching from
sector 0. A valid image is said to be found if a valid image
header is found, followed by a valid image. If a proper
image is not found, boot ROM will switch to DFU boot
mode.
Reserved 0 1 0 0 Reserved for testing.
NOR flash 1 0 1 Boot from parallel NOR flash connected to
EBI_NSTCS_1.
[1]
UART 1 1 0 Boot ROM tries to download boot image from UART
((115200 - 8 - n -1) assuming 12 MHz FFAST clock).
Test 1 1 1 Boot ROM is testing ISRAM using memory pattern test.
Switches to UART boot mode on receiving three ASCI
dots ("...") on UART.