Datasheet
LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 20 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
• Contains UTMI+ compliant transceiver (PHY).
• Supports interrupts.
• This module has its own, integrated DMA engine.
6.11 DMA controller
The DMA controller can perform DMA transfers on the AHB without using the CPU.
This module has the following features:
• Supported transfer types:
Memory to memory copy
– Memory can be copied from the source address to the destination address with a
specified length, while incrementing the address for both the source and
destination.
Memory to peripheral
– Data is transferred from incrementing memory to a fixed address of a peripheral.
The flow is controlled by the peripheral.
Peripheral to memory
– Data is transferred from a fixed address of a peripheral to incrementing memory.
The flow is controlled by the peripheral.
• Supports single data transfers for all transfer types.
• Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
• The DMA controller has 12 channels.
• Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
• Supports byte, half-word, and word transfers and correctly aligns them over the AHB
bus.
• Compatible with ARM flow control for single requests, last single requests, terminal
count info, and DMA clearing.
• Supports swapping endian property of the transported data.
Table 9: Peripherals that support DMA
Peripheral name Supported transfer types
NAND flash controller/AES decryption engine
[1]
Memory to memory
SPI Memory to peripheral and peripheral to memory
MCI Memory to peripheral and peripheral to memory
LCD interface Memory to peripheral
UART Memory to peripheral and peripheral to memory
I
2
C0/1-bus interfaces Memory to peripheral and peripheral to memory