Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 21 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
[1] AES decryption engine is available on LPC3143 only.
6.12 Interrupt controller
The interrupt controller collects interrupt requests from multiple devices, masks interrupt
requests, and forwards the combined requests to the processor. The interrupt controller
also provides facilities to identify the interrupt requesting devices to be served.
This module has the following features:
• The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
• Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM
core. The ARM core supports two distinct levels of priority on all interrupt sources,
FIQ for high priority interrupts and IRQ for normal priority interrupts.
• Software interrupt request capability associated with each request input.
• Visibility of interrupts request state before masking.
• Support for nesting of interrupt service routines.
• Interrupts routed to IRQ and to FIQ are vectored.
• Level interrupt support.
The following blocks can generate interrupts:
• NAND flash controller
• USB 2.0 HS OTG
• Event router
• 10 bit ADC
• UART
• LCD interface
• MCI
• SPI
• I
2
C0-bus and I
2
C1-bus controllers
• Timer 0, timer 1, timer 2, and timer 3
• I
2
S transmit: I2STX_0 and I2STX_1
• I
2
S receive: I2SRX_0 and I2SRX_1
• DMA
6.13 Multi-layer AHB
The multi-layer AHB is an interconnection scheme based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.
I
2
S0/1 receive Peripheral to Memory
I
2
S0/1 transmit Memory to peripheral
PCM interface Memory to peripheral and peripheral to memory
Table 9: Peripherals that support DMA …continued
Peripheral name Supported transfer types