Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 26 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
– Each base clock can be programmed to have any one of the clock sources as an
input clock.
– Fractional dividers can be used to divide a base clock by a fractional number to a
lower clock frequency.
– Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
output clock.
• Register interface to reset all modules under software control.
• Based on the input of the Watchdog timer (see also Section 6.16), the CGU can
generate a system-wide reset in the case of a system stall.
6.16 Watchdog Timer (WDT)
The watchdog timer can be used to generate a system reset if there is a CPU/software
crash. In addition the watchdog timer can be used as an ordinary timer. Figure 7
shows
how the watchdog timer module is connected in the system.
This module has the following features:
• In the event of a software or hardware failure, generates a chip-wide reset request
when its programmed time-out period has expired (output m1).
• Watchdog counter can be reset by a periodical software trigger.
The LPC3141/3143 has 11 clock domains (n = 11). The number of fractional dividers m depends on the clock domain.
Fig 6. CGU block diagram
OSCILLATOR
I2SRX_BCK0
I2SRX_WS0
I2SRX_BCK1
I2SRX_WS1
BASE
I
2
S/AUDIO
PLL
EXTERNAL
CRYSTAL
SYSTEM
PLL
002aae916
CLOCK DOMAIN 0
CLOCK DOMAIN n
FRACTIONAL
DIVIDER 0
FRACTIONAL
DIVIDER m
clock resources clock outputs
SWITCHBOX
subdomain clocks
to modules