Datasheet

LPC3141_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 4 June 2012 7 of 69
NXP Semiconductors
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
USB_DM N2 SUP3 AIO - AIO1 USB D connection with integrated 45 
termination resistor.
USB_VDDA12_PLL L1 SUP1 Supply - PS3 USB PLL supply.
USB_VDDA33_DRV M2 SUP3 Supply - PS3 USB analog supply for driver.
USB_VDDA33 P1 SUP3 Supply - PS3 USB analog supply for PHY.
USB_VSSA_TERM L3 - Ground - CG1 USB analog ground for clean reference for
on chip termination resistors.
USB_GNDA N1 - Ground - CG1 USB analog ground.
USB_VSSA_REF K4 - Ground - CG1 USB analog ground for clean reference.
JTAG
JTAGSEL N11 SUP3 DI I:PD DIO1 JTAG selection. Controls output function of
SCAN_TDO and ARM_TDO signals. Must
be LOW during power-on reset.
TDI K9 SUP3 DI I:PU DIO1 JTAG data input.
TRST_N P13 SUP3 DI I:PD DIO1 JTAG TAP Controller Reset Input. Must be
LOW during power-on reset.
TCK M14 SUP3 DI I:PD DIO1 JTAG clock input.
TMS P10 SUP3 DI I:PU DIO1 JTAG mode select input.
SCAN_TDO F10 SUP3 DO O/Z DIO1 JTAG TDO signal from scan TAP controller.
Pin state is controlled by JTAGSEL.
ARM_TDO E11 SUP3 DO O DIO1 JTAG TPO signal from ARM926 TAP
controller.
BUF_TRST_N F11 SUP3 DO O DIO1 Buffered TRST_N out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
BUF_TCK D13 SUP3 DO O DIO1 Buffered TCK out signal. Used for connecting
an on board TAP controller (FPGA, DSP,
etc.).
BUF_TMS D14 SUP3 DO O DIO1 Buffered TMS out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
UART
mUART_CTS_N
[4][5]
N13 SUP3 DI/GPIO I DIO1 UART clear to send (active LOW).
mUART_RTS_N
[4][5]
P14 SUP3 DO/GPIO O DIO1 UART ready to send (active LOW).
UART_RXD
[4]
P12 SUP3 DI/GPIO I DIO1 UART serial input.
UART_TXD
[4]
N12 SUP3 DO/GPIO O DIO1 UART serial output.
I
2
C-bus master/slave interface
I2C_SDA0 C10 SUP3 DIO I IICD I
2
C0-bus serial data line.
I2C_SCL0 D10 SUP3 DIO I IICC I
2
C0-bus serial clock line.
I2C_SDA1
[4]
E12 SUP3 DIO O DIO1 I
2
C1-bus serial data line.
I2C_SCL1
[4]
E13 SUP3 DIO O DIO1 I
2
C1-bus serial clock line.
Table 4. Pin description
…continued
Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
Pin name BGA
Ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description