Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 208 (12x12) 16/32-Bit 180 MHz I/O number 10

AFT

DRAFT

RAFT

DRAFT

DRA

T DRAF

RAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT

RAFT DRA

T DRAFT DRAFT DRAFT DRA

1. General description

The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB

2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an

integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and

parallel interfaces in a single chip targeted at consumer, industrial, medical, and

communication markets. To optimize system power consumption, the LPC3152/3154

have multiple power domains and a very flexible Clock Generation Unit (CGU) that

provides dynamic clock gating and scaling.

The LPC3152/3154 are implemented as a multi-chip module with two side-by-side dies,

one for digital functions and one for analog functions, which include Power Supply Unit

(PSU), audio codec, RTC, and Li-ion battery charger.

2. Features and benefits

2.1 Key features

 CPU platform

 180 MHz, 32-bit ARM926EJ-S

 16 kB D-cache and 16 kB I-cache

 Memory Management Unit (MMU)

 Internal memory

 192 kB embedded SRAM

 External memory interface

 NAND flash controller with 8-bit ECC and AES decryption engine (LPC3154 only)

 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM

 Security

 AES decryption engine (LPC3154 only)

 Secure one-time programmable memory for AES key storage and customer use

 128 bit unique ID per device for DRM schemes

 Communication and connectivity

 High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY

 Two I

S-bus interfaces

 Integrated master/slave SPI

 Two master/slave I

C-bus interfaces

 Fast UART

 Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA

LPC3152/3154

ARM926EJ microcontrollers with USB High-speed OTG,

SD/MMC, NAND flash controller, and audio codec

Rev. 0.12 — 27 May 2010 Preliminary data sheet

Summary of content (88 pages)

PAGE 1
R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, NAND flash controller, and audio codec R R R D D D F FT FT A A Preliminary data sheet A Rev. 0.12 — 27 May 2010 D D D D D LPC3152/3154 D FT FT A A R R D D D R A FT D R 1. General description A The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.
PAGE 2
D D R R R R R D D D FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D Three-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface Integrated audio codec with stereo ADC and Class AB headphone amplifier System functions Dynamic clock gating and scaling Multiple power domains Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB On the LPC3154 only: secur
PAGE 3
D D R R R R D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R Temperature range LPC3152FET208 192 kB yes no Device/ Host/OTG 3 yes yes 208 −40 °C to +85 °C LPC3154FET208 192 kB yes yes Device/ Host/OTG 3 yes yes 208 −40 °C to +85 °C FT MCI Pins SDHC/ SDIO/ CE-ATA FT A A R NAND Security High-speed 10-bit Audio Flash engine USB ADC codec, Controller AES channels PSU, RTC, Li-ion charger D D R A FT D R A Rev. 0.
PAGE 4
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 4. Block diagram FT FT FT FT FT LPC3152/3154 NXP Semiconductors D FT FT A A R R D JTAG D D R A R INSTRUCTION CACHE 16 kB A DATA CACHE 16 kB D ARM926EJ-S master master USB 2.
PAGE 5
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 5.1 Pinning A FT FT A A R R D D D 5. Pinning information FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R A FT 4 6 5 8 7 9 10 12 14 16 11 13 15 17 A 3 R 2 1 D ball A1 index area A B C D E F G H LPC3152/ LPC3154 J K L M N P R T U 002aae464 Transparent top view Fig 2.
PAGE 6
R R R R R FT D D R R FT FT FT A A A D D R A - Row E 1 VSSE_IOA 2 EBI_D_12 3 EBI_D_7 4 EBI_D_6 14 HP_VREF 15 RSTIN_N 16 PSU_VBAT 17 PSU_VOUT3 Row F 1 n.c. 2 EBI_D_13 3 EBI_D_5 4 EBI_D_4 14 TDO 15 DAC_VREFN 16 DAC_VREFP 17 PSU_VBAT2 Row G 1 n.c. 2 EBI_D_14 3 n.c.
PAGE 7
D D R R R R R D D D A R A FT D R A FT D R A FT D R A USB_DP 2 USB_GNDA 3 USB_VDDA33_DRV 4 mLCD_DB_12 5 mLCD_DB_7 6 mLCD_DB_2 7 mLCD_DB_0 8 mLCD_RW_WR 9 I2SRX_BCK0 10 TDI 11 mI2STX_CLK0 12 mI2STX_BCK0 13 mI2STX_DATA0 14 GPIO1 15 ADC_VINL 16 ADC_VREF 17 ADC_VREFP - - - Row U 1 n.c.
PAGE 8
A A A A A FT R A A FT FT D R R A FT FT FT A A R R D D D A F D FT FT A A R R D Pin Cell type Description [3] state after reset[2] R FT FT A A R R D D D D D R A [1] D R FT FT A A R R D D D Digital Application I/O function level FT FT FT FT TFB GA ball R R R R R Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
PAGE 9
A A A A A FT R A A FT FT D R R A FT FT FT A A R R D D D A F FT FT A A R R R D FT FT A A R R D Pin Cell type Description [3] state after reset[2] D D D D D R A [1] D R FT FT A A R R D D D Digital Application I/O function level FT FT FT FT TFB GA ball R R R R R Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
PAGE 10
D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT SUP3 Supply PS1 Peripheral supply VDDE_IOD G15 SUP3 Supply PS2 Analog die peripheral supply VSSE_IOA E1; N1 - Ground PG1 Peripheral ground NAND flash controller VSSE_IOB K1; U8 - Ground PG1 Peripheral ground LCD interface / SDRAM interface VSSE_IOC U16; A14; A5; - Ground PG1 Peripheral ground VSSE_IOD L14 - Ground PG2 Analog die peripheral ground m
PAGE 11
DIO1 I2S output word select mI2STX_CLK0[4] T11 SUP3 DO / GPIO O DIO1 I2S output serial clock A O R DO / GPIO D SUP3 D R12 I2S/Digital audio output General Purpose IO (IOCONFIG module) GPIO0[8] R13 SUP3 GPIO I:PD DIO1 General Purpose IO pin 0 (mode pin 0) GPIO1[8] T14 SUP3 GPIO I:PD DIO1 General Purpose IO pin 1 (mode pin 1) GPIO2[8] P12 SUP3 GPIO I DIO1 General Purpose IO pin 2 (mode pin 2/blinking LED) GPIO3 D12 SUP3 GPIO I DIO1 General Purpose IO pin 3 (connect
PAGE 12
R A A FT FT D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D D R A FT SUP4 DIO I DIO4 EBI Data I/O 14 H2 SUP4 DIO I DIO4 EBI Data I/O 15 EBI_DQM_0_NOE[4] K3 SUP4 DO O DIO4 EBI read enable (active LOW) EBI_NWE[4] K4 SUP4 DO O DIO4 EBI write enable (active LOW) NAND_NCS_0[4] L2 SUP4 DO O DIO4 EBI chip enable 0 NAND_NCS_1[4] L3 SUP4 DO O DIO4 EBI chip enable 1 NAND_NCS_2[4] L4 SUP4 DO O DIO4 EBI chip enable 2 NAND_NCS_3[4] M2 SUP4
PAGE 13
A A A A A FT FT D R FT D F FT A A R R D FT FT A A R R D Pin Cell type Description [3] state after reset[2] D D R A Supply CS1 PSU DCDC1 supply input R PSU stop signal input (active HIGH) D AIO2 FT I A D FT SUP6 A H17 R PSU_VBAT1 D AIO R FT FT SUP3 D A A D15 A FT R R PSU_STOP R A D D [1] D R FT FT A A R R D D D Digital Application I/O function level FT FT FT FT TFB GA ball R R R R R Table 4.
PAGE 14
R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D R A FT R A Voltage range Related supply pins SUP1 1.0 V to 1.3 V VDDI, VDDA12, Digital core supply USB_VDDA12_PLL, VPP (read) SUP2 1.4 V or 1.8 V VDDI_AD, ADC_VDDA18 Digital core supply for the analog die functions SUP3 2.7 V to 3.6 V VDDE_IOC, VDDE_IOD, ADC10B_VDDA33, ADC_VDDA33, DAC_VDDA33, HP_VDDA33, USB_VDDA33_DRV, USB_VDDA33, VPP (write) Peripheral supply SUP4 1.65 V to 1.95 V (in 1.8 V mode) VDDE_IOA 2.
PAGE 15
R R R R R A A A A A R R A F A FT D A FT D R - D Peripheral ground R vsse R PG1 D - D - Core ground FT Core ground vssis FT vssco CG2 A CG1 A - R Peripheral supply D vdde FT PS2 A - FT R R Peripheral supply A D D vdde3v3 R R FT FT PS1 D D A A Description FT FT R R Function A A D D I/O pad name Type FT D R FT FT A A R R D D D Cell types FT FT FT FT Table 6: D D D D D LPC3152/3154 NXP Semiconductors A 6.
PAGE 16
D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 6.
PAGE 17
R R R R R A A A A A D R R A A FT A F FT D R FT FT A A R D D 0x0020 - 0x002F D RTC FT 0x0010 - 0x001F R A A 0x0000 - 0x000F Audio codec D R R PSU/Li-ion charger R A D D Address offset D R FT FT A A R R D D D Block FT FT FT FT A A R R D D D Analog die register addresses (I2C1 slave device address 0x0C) FT FT FT FT FT Table 7. D D D D D LPC3152/3154 NXP Semiconductors R A FT D R A 6.
PAGE 18
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D AHB MULTI-LAYER MATRIX D D R A FT D R A BUFFER CONTROLLER AES DECODER(1) DMA transfer request ECC ENCODER/ DECODER NAND INTERFACE 002aae083 (1) AES decoder available on LPC3154 only. Fig 4.
PAGE 19
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F D FT FT A A R R D – Error correction statistics distributed to ARM using interrupt scheme. D FT FT A A R R D D – Interrupts generated after completion of error correction task with three interrupt registers. D D – Interface is compatible with the ARM External Bus Interface (EBI). R A FT D 6.
PAGE 20
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D The EBI module acts as multiplexer with arbitration between the NAND flash and the SDRAM/SRAM memory modules connected externally through the MPMC. FT A A R R D D D 6.6 External Bus Interface (EBI) FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R The main purpose for using the EBI module is to save external pins.
PAGE 21
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The boot ROM determines the boot mode based on the reset state of the GPIO0, GPIO1, and GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be low during power-on reset, see UM10315 JTAG chapter for details.
PAGE 22
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The MCI controller interface can be used to access memory cards according to the Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives.
PAGE 23
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D USB-IF TestID for Hi-speed peripheral silicon and embedded host silicon: 40720018 FT A A R R D D D • This module has its own, integrated DMA engine. FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D 6.11 DMA controller R A FT The DMA Controller can perform DMA transfers on the AHB bus without using the CPU.
PAGE 24
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The interrupt controller collects interrupt requests from multiple devices, masks interrupt requests, and forwards the combined requests to the processor. The interrupt controller also provides facilities to identify the interrupt requesting devices to be served. F FT FT A A R R D D D 6.
PAGE 25
D D R R R R D R R A A D R R A FT FT FT A A R R D D D R F D FT FT A A R R D USB-OTG AHB MASTER A FT FT A A R R D D D D D D-CACHE FT FT FT FT A A R R D D D I-CACHE FT FT FT FT FT ARM 926EJ-S A A A A A DMA R D D D LPC3152/3154 NXP Semiconductors R A 3 2 D 1 FT master 0 R 0 A slave AHB-APB BRIDGE 0 0 1 EVENT ROUTER 1 AHB-APB BRIDGE 1 0 2 AHB-APB BRIDGE 2 3 AHB-APB BRIDGE 3 4 AHB-APB BRIDGE 4 0 1 PCM LCD 0 6 SYST
PAGE 26
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix).
PAGE 27
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Within most clock domains, the output clocks are again grouped into one or more subdomains. All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock.
PAGE 28
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D • Based on the input of the Watchdog timer (see also Section 6.16), the CGU can generate a system-wide reset in the case of a system stall.
PAGE 29
D D R R R R R D D D A A A A A D R R A A FT R F FT FT A A A D FT FT A A R R D IRQ D R R CGU R A D D m1 WDT APB FIQ INTERRUPT CONTROLLER D R FT FT A A R R D D D EVENT ROUTER FT FT FT FT A A R R D D D m0 FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D reset R A FT D R A 002aae086 Fig 7. Block diagram of the Watchdog Timer 6.
PAGE 30
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake-up the system from suspend mode (with all clocks deactivated). F FT FT A A R R D D D 6.
PAGE 31
D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D The random number generator generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. FT A A R R D D D 6.
PAGE 32
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The SPI/SSI-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transfers. D FT FT A A R R D This module has the following features: FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R • Supports Motorola SPI frame format with a word size of 8/16 bits.
PAGE 33
D D R R R R D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT Receive and transmit DMA handshaking using a request/clear protocol. D R Interrupt generation per frame. A The IOM (ISDN Oriented Modular) interface is primarily used to interconnect telecommunications ICs providing ISDN compatibility. It delivers a symmetrical full-duplex communication link containing user data, control/programming lines, and status channels.
PAGE 34
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R F D FT FT A A R R D • Interrupt support. • Supports DMA transfers (single). • Four modes of operation: A FT FT A A R R D D • Fast mode (400 kHz SCL with 24 MHz APB clock; 325 kHz with12 MHz APB clock; 175 kHz with 6 MHz APB clock).
PAGE 35
R R R R R A A A A A D R R A A FT F EBI_A_4 A LCD_DB_4 D R R D A FT FT mLCD_DB_4 A LCD_DB_3 — LCD bidirectional data line 3. FT EBI_A_3 FT LCD_DB_3 R A A mLCD_DB_3 D R R Description R A D D Alternate signal D R FT FT A A R R D D D Default signal FT FT FT FT A A R R D D D Pin descriptions of multiplexed pins Pin name FT FT FT FT FT Table 11. D D D D D LPC3152/3154 NXP Semiconductors D D EBI_A_3 — EBI address line 3.
PAGE 36
R R R R R A A A A A D R R A A FT F EBI_A_4 A LCD_DB_4 D R R D A FT FT mLCD_DB_4 A LCD_DB_3 — LCD bidirectional data line 3. FT EBI_A_3 FT LCD_DB_3 R A A mLCD_DB_3 D R R Description R A D D Alternate signal D R FT FT A A R R D D D Default signal FT FT FT FT A A R R D D D Pin descriptions of multiplexed pins Pin name FT FT FT FT FT Table 11. D D D D D LPC3152/3154 NXP Semiconductors D D EBI_A_3 — EBI address line 3.
PAGE 37
FT R A A FT FT D R R A FT FT FT A A R R D D D R MCI_DAT_4 NAND_RYBN0 — NAND flash controller Read/Not busy signal 0. F FT FT Description A A A R R D D D D FT FT A A R R D D D NAND_RYBN0 D R FT FT A A R R D D D Alternate signal NAND flash related pin multiplexing mNAND_RYBN0 FT FT FT FT Default signal A A A A A Pin descriptions of multiplexed pins Pin name R R R R R Table 11.
PAGE 38
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT 16 data 3 A data control R 16 EBI_A_0_ALE EBI_A_1_CLE D 2 address EBI_A_[1:0] 2 data D 2 FT control (ALE, CLE) A NAND FLASH INTERFACE R EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE control D control NAND_NCS_[0:3] NAND_RYBN[0:3] FT A A R R D LPC31xx FT FT FT FT FT LPC3152/3154 NXP Semiconducto
PAGE 39
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D 2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage (SUP4) can be different from the LCD supply voltage (SUP8). D FT FT A A R R D 6.
PAGE 40
D D R R R R R D D D D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R FT FT A A R D D – analog inputs/outputs R A FT – Analog Volume Control (AVC) D R – Stereo Digital-to-Analog Converter (SDAC) A • I2S and I2C interfaces on the analog die for communication with the digital die.
PAGE 41
R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D D A FT R F D FT FT A A R R D D D R Supports LSB justified words of 16, 18, 20 and 24 bits. A FT FT A A R R D D D Transmit output supports master mode. R R FT FT A A R R D D D Receive input supports master mode and slave mode.
PAGE 42
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R FT FT A A R D D RTC_CLK32 R REAL-TIME CLOCK F D D FSLOW_OUT ANALOG DIE A FT FT A A R R D D D FSLOW_IN LPC3152/3154 FT FT FT FT FT LPC3152/3154 NXP Semiconductors A RTC_BACKUP FT RTC_VDD36 D R A RTC_INT from USB_VBUS ADC_VINR, ADC_VINL, ADC_MIC, ADC_ TINR, ADC_TINL ADC_VREFP, ADC_VREFN PSU_PLAY PSU_STOP ANALOG INPUT PSU_VOUT1 A
PAGE 43
D D R R R R R D D D D R R A A FT FT FT FT A A R R D D D D A FT R R FT FT A A R D D R A Selection for the up-sampling filter characteristics (sharp/slow roll-off). FT D Support for 2fs and 8fs input signals. R A Soft mute with a raised cosine function. The class AB headphone amplifier amplifies an analog input signal to levels appropriate for a headphone output.
PAGE 44
D D R R R R R D D D D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A MUX_R1 D R SDC FT PGA A right out ADC_MIC LNA PGA SDC SADC MUX_L1 MUX_L0 left out ADC_VINL PGA SDC ADC_TINL 002aae559 Fig 12. Stereo ADC for audio This module has the following features: Three input options: line-in (stereo), tuner-in (stereo), microphone-in (mono).
PAGE 45
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D • The nominal charge current is programmed with an external program-resistor. This allows the charge current to be adapted to the USB enumeration.
PAGE 46
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R F D FT FT A A R R D DIGITAL DIE A FT FT A A R R D D D LPC3152/3154 D D R FT USB_VBUS A SUP5 D R A SUP4/8 3.3 V MODE LPC3152/3154 ANALOG DIE SUP3 PSU_VBUS PSU_VOUT1 PSU_VBAT1 PSU_VBAT2 PSU_VOUT2 PSU SUP1 PSU_VBAT PSU_VOUT3 UOS_VBUS SUP4/8 1.
PAGE 47
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D A FT R A F FT FT A A R R D D D D FT FT A A R R D 7.6 Real-Time Clock (RTC) R R FT FT A A R R D D D • Provides ‘Supply_OK’ detection connected to the system reset signal. FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D The Real-Time Clock module keeps track of the actual date and time, also when the system is switched off.
PAGE 48
D D R R R R R D D D D R R A A D R R A FT FT FT A A R R D D D R R FT FT A A R D Unit A Max R Typ D Min FT D −0.5 - +3.6 V Vo output voltage −0.5 - +3.6 V Io output current - 4 - mA −40 25 125 °C −65 - +150 °C −40 +25 +85 °C −500 - +500 V machine model −100 - +100 V charged device model - 500 - V VDDE_IOC = 3.
PAGE 49
D D R R R R R D D D D R R A A R A FT R on pin VDDA12; for 12 MHz oscillator (SUP1) 1.0 1.2 1.3 VDD(ADC) ADC supply voltage on pin ADC10B_VDDA33; for 10-bit ADC (SUP 3) 2.7 3.3 3.6 V Vprog(pf) polyfuse programming voltage on pin VPP; write 3.0 3.3 3.6 V on pin VPP; read 1.1 - 1.3 V bus supply voltage on pin USB_VBUS (SUP5) - 5.0 - V on pin USB_VDDA33 (SUP 3) 3.0 3.3 3.6 V on pin USB_VDDA33_DRV (SUP 3); driver 2.7 3.3 3.6 V on pin USB_VDDA12_PLL (SUP1) 1.
PAGE 50
D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R 50 SUP3 [1] 50 μA - - pF - VDD(IO) V A FT μA FT D D R LOW-level output voltage 1.8 V mode V 3.3 V mode VDD(IO) − 0.26 V SUP3; IOH = 6 mA VDD(IO) − 0.26 - - V SUP3; IOH = 30 mA VDD(IO) − 0.38 - - V V 0.65 V SUP4; SUP8 outputs; IOL = 4 mA 1.8 V mode 3.
PAGE 51
R R R R R D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R OFF-state output current VO = 0 V; VO = VDD; no pull-up/down - - 7.25 μA VIH HIGH-level input voltage [1] 0.7VDDE_IOC - - V VIL LOW-level input voltage [1] - - 0.3VDDE_IOC V Vhys hysteresis voltage 0.1VDDE_IOC - - V VOL LOW-level output voltage IOLS = 3 mA - - 0.298 V ILI input leakage current VDDE voltage domain; Tamb = 25 °C [1] - 1.
PAGE 52
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 14.
PAGE 53
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT gain error EG FT A A R R D D D D FT FT A A R R D offset error EO FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R 1023 A FT D R 1022 A 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB
PAGE 54
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D D Rvsi D AD10B_GPA[0:2] FT tbd kΩ R ADCSAMPLE FT A A R R D LPC3152/3154 A FT tbd pF D tbd pF R A VEXT VSSA 002aae563 Fig 15. Suggested 10-bit ADC interface 9.2 Analog die Table 15.
PAGE 55
D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R output voltage generated from PSU_VBAT (programmable in 8 levels) 0.9 1.04 1.4 V generated from PSU_VBUS (LDO1 on) 1.15 1.2 1.25 V −50 - +50 mV R FT FT A A R D D R A FT D R A IO output current on pin PSU_VOUT2 - - 80 mA IL(LDO)(max) maximum LDO load current on LDO2 80 100 - mA output voltage generated from either PSU_VBAT or PSU_VBUS (programmable in 2 levels) - 1.4 1.
PAGE 56
D D R R R R R D D D A A A A A D R R A A D R R A FT FT FT A A R R D D D R A D D Conditions Typ Max ADC analog supply current (3.3 V) per mono ADC; normal operation 2.2 - mA Unit IDDA(ADC)(1V8) ADC analog supply current (1.
PAGE 57
D D R R R R R D D D D R R A A FT R D 1 2.8676 39.80566352 2.8 3.6016 2 2.864 56.80015231 3.598 - 3 2.8605 66.22816876 2.8498 79.23374865 6.793 3.5999 7 2.8462 81.47256753 7.59 3.5995 8 2.8426 83.23802841 8.388 3.5992 9 2.83991 84.63671469 9.231 3.5988 10 2.8542 85.9167695 13.32 3.597 15 2.8549 89.37941277 17.368 3.595 20 2.837 90.87420537 25.59 3.591 30 2.8198 92.056375145 A 6 R 3.6003 D 5.994 D 76.27057345 FT 72.18953182 2.
PAGE 58
D R R A A FT D 1.072 29.70184007 1.357 3.6022 2 1.069 43.7381119 1.71 3.6021 3 1.068 52.0164407 2.063 3.6019 4 1.067 57.43723586 2.415 3.6018 5 1.0664 61.29900313 2.77 3.6016 6 1.0655 64.08102616 3.122 3.6015 7 1.0647 66.28404084 3.472 3.6013 8 1.0638 68.06297931 3.822 3.6011 9 1.0628 69.49734136 4.172 3.601 10 1.0619 70.68319948 5.7 3.6003 15 1.0218 74.68675856 7.292 3.5997 20 1.0258 78.15913105 10.466 3.5983 30 1.0151 80.
PAGE 59
D D R R R R D R R A A FT FT FT FT A A R R D D D D A FT R R A Unit FT FT A Max R Typ V - mA Rext = 1.00 kΩ 95 100 105 mA Rext = 400Ω 237.5 250 262.5 mA battery voltage rising - 2.8 - V battery voltage falling - 2.7 - V After compensation using cs_bits 4.158 4.2 4.242 V - 4.05 - V D 4.
PAGE 60
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 10.1 Digital die A FT FT A A R R D D D 10. Dynamic characteristics FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R FT D Intel 8080 mode R A 10.1.1.1 A 10.1.1 LCD controller Table 21.
PAGE 61
R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A - 1 × LCDCLK - ns - 2 × LCDCLK - ns 5 × LCDCLK - ns 2 - 5 ns tf fall time 2 - 5 ns tsu(D) data input set-up time - - ns th(D) data input hold time - - ns td(QV) data output valid delay time - −1 × LCDCLK - ns tdis(Q) data output disable time - 2 × LCDCLK - ns tw(en) enable pulse width read cycle - 2 × LCDCLK - ns write c
PAGE 62
R R R R R A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A Unit clock cycle time - 5 × LCDCLK - ns HIGH clock pulse width [1] - 3 × LCDCLK - ns tw(clk)L LOW clock pulse width [1] - 2 × LCDCLK - ns tr rise time 2 - 5 ns tf fall time 2 - 5 ns tsu(A) address set-up time - 3 × LCDCLK - ns ns - ns th(D) data input hold time - - ns tsu(S) chip select set-up time - 3 × LCDCLK - ns th(S)
PAGE 63
D D R R R R D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Typ Max Unit −1.8 0 4 ns D Min D Conditions FT FT FT FT FT Table 24. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = −40 °C to +85 °C, unless otherwise specified; VDD(IO) = 1.8 V and 3.3 V (SUP8). Parameter A A A A A 10.1.
PAGE 64
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D EBI_NSTCS_X FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R A FT tCSLAV D R A EBI_A_[15:0] tCSHOEH tOELAV EBI_DQM_0_NOE tOELOEH tCSLOEL tOEHANV tBLSLAV tCSHBLSH EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 tBLSLBLSH tCSLBLSL tBLSHANV EBI_D_[15:0] th(DQ) tsu(DQ) 002aae161 Fig 21.
PAGE 65
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D EBI_NSTCS_X FT FT FT FT FT LPC3152/3154 NXP Semiconductors D D R A FT tCSLAV D R A EBI_A_[15:0] tBLSHANV tCSLDV tWEHANV EBI_D_[15:0] tWELWEH tCSLWEL tWEHDNV tWELDV tBLSHDNV EBI_NWE tBLSLBLSH tCSLBLSL EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 002aae162 Fig 22.
PAGE 66
FT A FT R F D A A R R D 3.6 ns on pins EBI_NRAS_BLOUT, EBI_NCAS_BLOUT, EBI_NWE, EBI_NDYCS −0.1 - 3.6 ns on pins EBI_DQM_1, EBI_DQM_0_NOE 1.7 - 5 ns FT - FT 0.13 D D R A FT D R A address valid delay time [5] - - 5 ns th(A) address hold time [5] −0.
PAGE 67
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D TCLCL R A FT tCLCX D tCHCX R A EBI_CLKOUT td(o) EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS th(o) READ NOP NOP NOP td(o) READ NOP NOP th(o) EBI_DQMx th(A) EBI_A_[15:2] BANK, COLUMN tsu(D) th(D) EBI_D_[15:0] DATA n CAS LATE
PAGE 68
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors LPC3152_3154 Preliminary data sheet TCLCL tCLCX tCHCX EBI_CLKOUT td(o) th(o) EBI_CK
PAGE 69
D D R R R R R D D D A A A A A D R R A A FT R F FT FT A A A D FT FT A A R R D Unit [1][2][3] THCLK × (TREH) ns RE pulse width [1][2][3] THCLK × (TRP) ns WE HIGH hold time [1][2][3] THCLK × (TWH) ns tWP WE pulse width [1][2][3] THCLK × (TWP) ns tCLS CLE set-up time [1][2][3] THCLK × (TCLS) ns tCLH CLE hold time [1][2][3] THCLK × (TCLH) ns ALE set-up time [1][2][3] THCLK × (TALS) ns tALH ALE hold time [1][2][3] THCLK × (TALH) ns tCS CE set-up t
PAGE 70
D D R R R R D R R A A FT FT FT FT A A R R D D D D A FT R R A Unit FT FT A Max R Typ 12 25 MHz 45 50 55 % Cxtal crystal capacitance input; on pin FFAST_IN - - 2 pF output; on pin FFAST_OUT - - 0.74 pF μs Pdrive drive power 100 - 500 µW 10.2.2 SPI Table 28. Dynamic characteristics of SPI pins Tamb = −40 °C to +85 °C for industrial applications Parameter Min Typ Max Unit TSPICYC SPI cycle time 22.2 - - ns tSPICLKH SPICLK HIGH time 11.09 - 11.
PAGE 71
D D R R R R R D D D A A A A A D R R A A D R R A FT FT FT A A R R D D D A F FT FT A A R R R tSPICLKL D D D tSPICLKH FT FT FT FT A A R R D D D tSPICLK FT FT FT FT FT LPC3152/3154 NXP Semiconductors D FT FT A A R R D SCK (CPOL = 0) D D R A FT D SCK (CPOL = 1) R DATA VALID DATA VALID tSPIDSU MISO A tSPIOH tSPISEDV MOSI DATA VALID tSPIDH DATA VALID 002aad986 Fig 26.
PAGE 72
D D R R R R R D D D A A A A A D R R A A FT R F FT FT A A A D FT FT A A R R D tSPIDH D R R tSPIDSU R A D D tSPICLKL D R FT FT A A R R D D D tSPICLKH FT FT FT FT A A R R D D D tSPICLK FT FT FT FT FT LPC3152/3154 NXP Semiconductors SCK (CPOL = 0) D D R A FT D SCK (CPOL = 1) R DATA VALID A MOSI DATA VALID tSPIOH tSPISEDV MISO DATA VALID DATA VALID 002aad988 Fig 28.
PAGE 73
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D shifting edges FT FT FT FT FT LPC3152/3154 NXP Semiconductors D FT FT A A R R D SCK D D R A FT sampling edges D R A MOSI MISO tsu(SPI_MISO) 002aad326 Fig 30. MISO line set-up time in SSP Master mode LPC3152_3154 Preliminary data sheet All information provided in this document is subject to legal disclaimers.
PAGE 74
D D R R R R FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT Typ Max Unit D Min D Conditions FT A A R R D Table 30. Dynamic characteristics: I2S-interface pins Tamb = −40 °C to +85 °C for industrial applications Parameter A A A A A 10.2.3 I2S-interface Symbol R D D D LPC3152/3154 NXP Semiconductors R A FT common to input and output ns tf fall time 3.
PAGE 75
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D F FT FT A A A tr R R R tf D D D Tcy FT FT FT FT FT LPC3152/3154 NXP Semiconductors D FT FT A A R R D I2SRX_SCK D D R A tWL FT tWH D R A I2SRX_SDA tsu(D) thD) I2SRX_WS tsu(D) 002aad993 th2 Fig 32. I2S-bus timing (input) 10.2.4 I2C-bus Table 31. Dynamic characteristic: I2C-bus pins Tamb = −40 °C to +85 °C.
PAGE 76
D D R R R R R D D D A A A A A FT FT FT FT FT LPC3152/3154 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D SDA tf tHD;STA D tr R tLOW D tBUF A FT D SCL tHD;STA P S tHD;STA tHIGH tSU;DAT tSU;STA A S R P tSU;STO 002aad985 Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx (x = 0, 1). Fig 33.
PAGE 77
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D A F FT FT A A R R R D FT FT A A R R D Table 32. Dynamic characteristics: USB pins (high-speed) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(IO) (SUP3), unless otherwise specified. D D D 10.2.
PAGE 78
D D R R R R D R R A A FT A F R A FT D Unit D R at 0 dBFS; fin = 1 kHz; RL=16 Ω D Total harmonic distortion plus noise-to-signal ratio Max FT (THD+N)/S A 800 R - per channel; RL=16 Ω D HP unloaded output power FT FT output voltage R A A Po D R R Vo R A D D Typ D R FT FT A A R R D D D Min FT FT FT FT A A R R D D D Conditions FT FT FT FT FT Table 34.
PAGE 79
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 36. NXP Semiconductors LPC3152_3154 Preliminary data sheet 11.
PAGE 80
D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 12. Marking FT FT FT FT LPC3152/3154 NXP Semiconductors D FT FT A A R R D D LPC3152/3154 Marking D R Table 37. LPC3152/3154 BASIC_TYPE R A D Description FT Marking A Line A LPC3152_3154 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 0.
PAGE 81
D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 13. Package outline FT FT FT FT FT LPC3152/3154 NXP Semiconductors D FT A A R R D TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 12 x 12 x 0.
PAGE 82
D D R R R R D R R A A FT FIR Finite Input Response HP Headphones IOCONFIG Input Output Configuration ROM Read Only Memory IrDA Infrared Data Association JTAG Joint Test Action Group ISRAM Internal Static RAM Memory JTAG Joint Test Action Group LCD Liquid Crystal Display LDO Low Drop voltage Output regulator LNA Low-Noise Amplifier MMU Memory Management Unit NTC Negative Temperature Coefficient OTP One-Time Programmable Memory PCM Pulse Code Modulation PGA Programmabl
PAGE 83
R R R R R A A A A A FT FT D R A FT A F FT FT A A R R D D R D FT FT A A R R D D D R A FT USB 2.0 HS OTG Universal Serial Bus 2.
PAGE 84
D D R R R R D R R A A FT D A F FT FT A A R R R D FT FT A A R R D LPC3152_3154 v.0.12 Preliminary data sheet - LPC3152_3154_0.11 D Supersedes D Change notice R A D Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in Table 4. R A Document template updated. Digital I/O level for pin CLOCK_OUT corrected in Table 4. USB Hi-speed logo added. USB-IF TestID numbers added in Section 6.10.
PAGE 85
D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 16.1 Data sheet status A FT FT A A R R D D D 16. Legal information FT FT FT FT LPC3152/3154 NXP Semiconductors D D R Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development.
PAGE 86
D D R R R R R D D D A FT FT D D R A FT FT FT A A R R R D R A F FT FT A A R R D D whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semic
PAGE 87
D D R R R R D R R A A R A FT R FT FT D D R A R A 87 of 88 D © NXP B.V. 2010. All rights reserved. FT Rev. 0.12 — 27 May 2010 A A All information provided in this document is subject to legal disclaimers. R R Preliminary data sheet F D D System control registers . . . . . . . . . . . . . . . . 39 Audio Subsystem (ADSS) . . . . . . . . . . . . . . . 39 I2S0/1 digital audio input/output . . . . . . . . . . . 40 Functional description of the analog die blocks. . . . . . . . . . . .
PAGE 88
A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 85 85 85 85 86 86 87 FT FT FT FT D FT FT A A R R D D D R A FT D Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . .