Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 10 of 88
NXP Semiconductors
LPC3152/3154
VDDE_IOC U15;
A15;
A4;
SUP3 Supply PS1 Peripheral supply
VDDE_IOD G15 SUP3 Supply PS2 Analog die peripheral supply
VSSE_IOA E1;
N1
- Ground PG1 Peripheral ground NAND flash controller
VSSE_IOB K1;
U8
- Ground PG1 Peripheral ground LCD interface / SDRAM
interface
VSSE_IOC U16;
A14;
A5;
- Ground PG1 Peripheral ground
VSSE_IOD L14 - Ground PG2 Analog die peripheral ground
LCD interface
mLCD_CSB
[4]
R8 SUP8 DO O DIO4 LCD chip select (active LOW)
mLCD_E_RD
[4]
P7 SUP8 DO O DIO4 LCD: 6800 enable, 8080 read enable (active
HIGH)
mLCD_RS
[4]
R7 SUP8 DO O DIO4 LCD: instruction register (LOW)/ data register
(HIGH) select
mLCD_RW_WR
[4]
T8 SUP8 DO O DIO4 LCD: 6800 read/write select,8080 write
enable (active HIGH)
mLCD_DB_0
[4]
T7 SUP8 DIO O DIO4 LCD Data 0
mLCD_DB_1
[4]
P8 SUP8 DIO O DIO4 LCD Data 1
mLCD_DB_2
[4]
T6 SUP8 DIO O DIO4 LCD Data 2
mLCD_DB_3
[4]
R6 SUP8 DIO O DIO4 LCD Data 3
mLCD_DB_4
[4]
U6 SUP8 DIO O DIO4 LCD Data 4
mLCD_DB_5
[4]
P6 SUP8 DIO O DIO4 LCD Data 5
mLCD_DB_6
[4]
R5 SUP8 DIO O DIO4 LCD Data 6
mLCD_DB_7
[4]
T5 SUP8 DIO O DIO4 LCD Data 7
mLCD_DB_8
[4]
U5 SUP8 DIO O DIO4 LCD Data 8 / 8-bit Data 0
mLCD_DB_9
[4]
P5 SUP8 DIO O DIO4 LCD Data 9 / 8-bit Data 1
mLCD_DB_10
[4]
P4 SUP8 DIO O DIO4 LCD Data 10 / 8-bit Data 2
mLCD_DB_11
[4]
U4 SUP8 DIO O DIO4 LCD Data 11 / 8-bit Data 3
mLCD_DB_12
[4]
T4 SUP8 DIO O DIO4 LCD Data 12 / 8-bit Data 4 / 4-bit Data 0
mLCD_DB_13
[4]
U3 SUP8 DIO O DIO4 LCD Data 13 / 8-bit Data 5 / 4-bit Data 1 /
serial clock output
mLCD_DB_14
[4]
U2 SUP8 DIO O DIO4 LCD Data 14 / 8-bit Data 6 / 4-bit Data 2 /
serial data input
mLCD_DB_15
[4]
R4 SUP8 DIO O DIO4 LCD Data 15 / 8-bit Data 7 / 4-bit Data 3 /
serial data output
I
2
S/Digital audio input
I2SRX_DATA0
[4]
P9 SUP3 DI / GPIO I DIO1 I
2
S input serial data receive
Table 4. Pin description
…continued
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
TFBGA pin name TFB
GA
ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description