Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 11 of 88
NXP Semiconductors
LPC3152/3154
I2SRX_BCK0
[4]
T9 SUP3 DIO / GPIO I DIO1 I
2
S input bitclock
I2SRX_WS0
[4]
R9 SUP3 DIO / GPIO I DIO1 I
2
S input word select
I
2
S/Digital audio output
mI2STX_DATA0
[4]
T13 SUP3 DO / GPIO O DIO1 I
2
S output serial data out
mI2STX_BCK0
[4]
T12 SUP3 DO / GPIO O DIO1 I
2
S output bitclock
mI2STX_WS0
[4]
R12 SUP3 DO / GPIO O DIO1 I
2
S output word select
mI2STX_CLK0
[4]
T11 SUP3 DO / GPIO O DIO1 I
2
S output serial clock
General Purpose IO (IOCONFIG module)
GPIO0
[8]
R13 SUP3 GPIO I:PD DIO1 General Purpose IO pin 0 (mode pin 0)
GPIO1
[8]
T14 SUP3 GPIO I:PD DIO1 General Purpose IO pin 1 (mode pin 1)
GPIO2
[8]
P12 SUP3 GPIO I DIO1 General Purpose IO pin 2 (mode
pin 2/blinking LED)
GPIO3 D12 SUP3 GPIO I DIO1 General Purpose IO pin 3 (connect to
PSU_STOP)
[5]
GPIO4 D11 SUP3 GPI I DIO1 General Purpose Input pin 4
mGPIO5
[4]
D7 SUP3 GPIO I DIO4 General Purpose IO pin 5
mGPIO6
[4]
B7 SUP3 GPIO I DIO4 General Purpose IO pin 6
mGPIO7
[4]
C7 SUP3 GPIO I DIO4 General Purpose IO pin 7
mGPIO8
[4]
D6 SUP3 GPIO I DIO4 General Purpose IO pin 8
mGPIO9
[4]
B6 SUP3 GPIO I DIO4 General Purpose IO pin 9
mGPIO10
[4]
C6 SUP3 GPIO I DIO4 General Purpose IO pin 10
External Bus Interface (NAND flash controller)
EBI_A_0_ALE
[4]
C4 SUP4 DO O DIO4 EBI Address Latch Enable (ALE)
EBI_A_1_CLE
[4]
A2 SUP4 DO O DIO4 EBI Command Latch Enable (CLE)
EBI_D_0
[4]
J3 SUP4 DIO I DIO4 EBI Data I/O 0
EBI_D_1
[4]
H3 SUP4 DIO I DIO4 EBI Data I/O 1
EBI_D_2
[4]
H4 SUP4 DIO I DIO4 EBI Data I/O 2
EBI_D_3
[4]
G4 SUP4 DIO I DIO4 EBI Data I/O 3
EBI_D_4
[4]
F4 SUP4 DIO I DIO4 EBI Data I/O 4
EBI_D_5
[4]
F3 SUP4 DIO I DIO4 EBI Data I/O 5
EBI_D_6
[4]
E4 SUP4 DIO I DIO4 EBI Data I/O 6
EBI_D_7
[4]
E3 SUP4 DIO I DIO4 EBI Data I/O 7
EBI_D_8
[4]
D3 SUP4 DIO I DIO4 EBI Data I/O 8
EBI_D_9
[4]
A3 SUP4 DIO I DIO4 EBI Data I/O 9
EBI_D_10
[4]
C2 SUP4 DIO I DIO4 EBI Data I/O 10
EBI_D_11
[4]
D2 SUP4 DIO I DIO4 EBI Data I/O 11
EBI_D_12
[4]
E2 SUP4 DIO I DIO4 EBI Data I/O 12
EBI_D_13
[4]
F2 SUP4 DIO I DIO4 EBI Data I/O 13
Table 4. Pin description …continued
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
TFBGA pin name TFB
GA
ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description