Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 13 of 88
NXP Semiconductors
LPC3152/3154
[1] Digital IO levels are explained in Tab le 5.
[2] I = input; I:PU = input with internal weak pull-up; I:PD = input with internal weak pull-down; O = output.
[3] Cell types are explained in Table 6
.
[4] Pin can be configured as GPIO pin in the IOCONFIG block.
[5] GPIO3 is driven HIGH if the boot process fails. It is recommended to connect GPIO3 to PSU_STOP, so that the LPC3152/3154 will be
powered down and further access prevented if the boot ROM detects an error.
[6] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can be selected to be used for their alternative function: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2).
[7] The polyfuses get unintentionally burned at random if VPP is powered to 2.3 V or greater before the VDDI is powered up to minimum
nominal voltage. This will destroy the sample, and it can be locked (security) and the AES key can be corrupted. For this reason it is
recommended that VPP be powered by SUP1 at power-on.
[8] To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see
UM10315 JTAG chapter for details.
PSU_STOP D15 SUP3 AIO I AIO2 PSU stop signal input (active HIGH)
PSU_VBAT1 H17 SUP6 Supply CS1 PSU DCDC1 supply input
PSU_VBAT2 F17 SUP6 Supply CS1 PSU DCDC2 supply input
PSU_VBAT E16 SUP6 Supply CS1 PSU Li-ion battery input
Li-Ion charger
CHARGE_VNTC J17 - AI AIO2 Charger NTC connection
CHARGE_VSS J15 - Ground CG1 Charger ground Li-Ion
CHARGE_CC_REF K15 - AO CS1 Charger constant current reference
CHARGE_VBUS J14 SUP5 Supply CS1 Charger 5 V supply
CHARGE_BAT_SENSE K17 - AI AIO2 Charger battery sense terminal
CHARGE_VBAT K16 SUP6 AO CS1 Charger positive battery terminal connection
USB charge pump (host mode)
UOS_VSS N17 - Ground CG1 USB charge pump ground
UOS_VBUS P15 SUP5 AO CS1 USB charge pump output to USB_VBUS
UOS_VBAT P16 SUP6 Supply CS1 USB charge-pump supply Li-ion battery input
UOS_CX2 P17 - AIO CS1 USB charge-pump capacitor terminal for
voltage converter
UOS_CX1 R17 - AIO CS1 USB charge-pump capacitor terminal for
voltage converter
Pulse Width Modulation module
PWM_DATA
[4]
D10 SUP3 DO/GPIO O DIO1 PWM output
Table 4. Pin description
…continued
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
TFBGA pin name TFB
GA
ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
[2]
Cell type
[3]
Description