Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 14 of 88
NXP Semiconductors
LPC3152/3154
[1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD interface must be the same, i.e. SUP4 and
SUP8 should be connected to the same rail. (See also Section 6.28.3
.).
Table 5: Supply domains
Supply
domain
Voltage range Related supply pins Description
SUP1 1.0 V to 1.3 V VDDI, VDDA12,
USB_VDDA12_PLL, VPP (read)
Digital core supply
SUP2 1.4 V or 1.8 V VDDI_AD, ADC_VDDA18 Digital core supply for the analog die
functions
SUP3 2.7 V to 3.6 V VDDE_IOC, VDDE_IOD,
ADC10B_VDDA33,
ADC_VDDA33, DAC_VDDA33,
HP_VDDA33,
USB_VDDA33_DRV,
USB_VDDA33, VPP (write)
Peripheral supply
SUP4 1.65 V to 1.95 V (in 1.8 V mode)
2.5 V to 3.6 V (in 3.3 V mode)
VDDE_IOA Peripheral supply for NAND flash interface
SUP5 4.5 V to 5.5 V PSU_VBUS, CHARGE_VBUS,
UOS_VBUS, USB_VBUS
USB VBUS voltage
SUP6 3.2 V to 4.2 V RTC_VDD36, PSU_VBAT1,
PSU_VBAT2, PSU_VBAT
Li-ion battery voltage
SUP7 1.8 V RTC_BACKUP Real-time clock voltage domain (generated
internally from SUP6)
SUP8 1.65 V to 1.95 V (in 1.8 V mode)
2.5 V to 3.6 V (in 3.3 V mode)
VDDE_IOB Peripheral supply for
SDRAM/SRAM/bus-based LCD
[1]
Table 6: Cell types
I/O pad name Type Function Description
DIO1 bspts3chp Digital input/output Bidirectional 3.3 V; 3-state output; 3 ns slew rate control; plain
input; CMOS with hysteresis; programmable pull-up, pull-down,
repeater.
DIO2 bpts5pcph Digital input/output Bidirectional 5 V; plain input; 3-state output; CMOS with
programmable hysteresis; programmable pull-up, pull-down,
repeater.
DIO3 bpts5pcph1v8 Digital input/output Bidirectional 1.8 V; plain input; 3-state output; CMOS with
programmable hysteresis; programmable pull-up, pull-down,
repeater.
DIO4 mem1
bsptz40pchp
Digital input/output Bidirectional 1.8 or 3.3 V; plain input; 3-state output; CMOS with
programmable hysteresis; programmable pull-up, pull-down,
repeater.
IICC iic3m4scl Digital input/output I
2
C-bus; clock signal; cell based ESD protection.
IICD iic3mvsda Digital input/output I
2
C-bus; data signal; cell based ESD protection.
AIO1 apio3v3 Analog input/output Analog cell; analog input/output; protection to external 3.3 V
supply rail.
AIO2 apio Analog input/output Analog pad; analog input/output.
AIO3 apiot5v Analog input/output Analog cell; analog input/output; 5 V tolerant pad-based ESD
protection.
CS1 vddco Core supply -
CS2 vddi Core supply -