Datasheet

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RAFT
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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 17 of 88
NXP Semiconductors
LPC3152/3154
6.3 JTAG
The JTAG interface allows the incorporation of the LPC3152/3154 in a JTAG scan chain.
This module has the following features:
• ARM926 debug access
• Boundary scan
• The ARM926 debug access can be permanently disabled through the JTAG security
bits in the One-Time Programmable memory (OTP) block.
6.4 NAND flash controller
The NAND flash controller is used as a dedicated interface to NAND flash devices.
Figure 4
shows a block diagram of the NAND flash controller module. The heart of the
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An error
correction encoder/decoder module allows for hardware error correction for support of
Multi-Level Cell (MLC) NAND flash devices. In the LPC3154, the NAND flash controller is
connected to the AES block to support secure (encrypted) code execution (see
Section 6.21
).
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects errors, and/or the AES decryption module can
decrypt data.
Table 7. Analog die register addresses (I
2
C1 slave device address 0x0C)
Block Address offset
PSU/Li-ion charger 0x0000 - 0x000F
Audio codec 0x0010 - 0x001F
RTC 0x0020 - 0x002F