Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 18 of 88
NXP Semiconductors
LPC3152/3154
This module has the following features:
• Dedicated NAND flash interface with hardware controlled read and write accesses.
• Wear leveling support with 516-byte mode.
• Software controlled command and address transfers to support wide range of flash
devices.
• Software control mode where the ARM is directly master of the flash device.
• Support for 8-bit and 16-bit flash devices.
• Support for any page size from 0.5 kB upwards.
• Programmable NAND flash timing parameters.
• Support for up to four NAND devices.
• Hardware AES decryption (LPC3154 only).
• Error Correction Module (ECC) for MLC NAND flash support:
– Reed-Solomon error correction encoding and decoding.
– Uses Reed-Solomon code words with 9-bit symbols over GF(2
9
), a total code word
length of 469 symbols, including 10 parity symbols, giving a minimum Hamming
distance of 11.
– Up to 8 symbol errors can be corrected per codeword.
– Error correction can be turned on and off to match the demands of the application.
– Parity generator for error correction encoding.
– Wear leveling information can be integrated into protected data.
(1) AES decoder available on LPC3154 only.
Fig 4. Block diagram of the NAND flash controller
002aae083
AHB MULTI-LAYER MATRIX
BUFFER
CONTROLLER
AES
DECODER
(1)
ECC
ENCODER/
DECODER
NAND INTERFACE
DMA transfer request