Datasheet

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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 19 of 88
NXP Semiconductors
LPC3152/3154
– Interrupts generated after completion of error correction task with three interrupt
registers.
– Error correction statistics distributed to ARM using interrupt scheme.
– Interface is compatible with the ARM External Bus Interface (EBI).
6.5 Multi-Port Memory Controller (MPMC)
The multi-port memory controller supports the interface to different memory types, for
example:
• SDRAM
• Low-power SDRAM
• Static memory interface
This module has the following features:
• Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM.
• Address line supporting up to 128 MB (two 64Mx8 devices connected to a single chip
select) of dynamic memory.
• The MPMC has two AHB interfaces:
a. an interface for accessing external memory.
b. a separate control interface to program the MPMC. This enables the MPMC
registers to be situated in memory with other system peripheral registers.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance, particularly for
un-cached processors.
• Static memory features include:
– asynchronous page mode read
– programmable wait states
– bus turnaround delay
– output enable, and write enable delays
– extended wait
• One chip select for synchronous memory and two chip selects for static memory
devices.
• Power-saving modes.
• Dynamic memory self-refresh mode supported.
• Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts.
• Support for all AHB burst types.
• Little and big-endian support.
• Support for the External Bus Interface (EBI) that enables the memory controller pads
to be shared.