Datasheet

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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 21 of 88
NXP Semiconductors
LPC3152/3154
The boot ROM determines the boot mode based on the reset state of the GPIO0, GPIO1,
and GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be low during power-on reset, see UM10315 JTAG chapter
for details.
Table 9
shows the various boot modes supported on the LPC3152/3154. If the boot
process fails (e.g. due to tampering with security), the boot code drives pin GPIO3 HIGH.
It is recommended to connect the GPIO3 pin to PSU_STOP, so that the LPC3152/3154
will be powered down and further access prevented when the boot ROM detects an error.
[1] For security reasons this mode is disabled when JTAG security feature is used.
6.8 Internal RAM memory
The ISRAM (Internal Static Memory Controller) module is used as controller between the
AHB bus and the internal RAM memory. The internal RAM memory can be used as
working memory for the ARM processor and as temporary storage to execute the code
that is loaded by boot ROM from external devices such as SPI-flash, NAND flash and
SD/MMC cards.
This module has the following features:
• Capacity of 192 kB
• Implemented as two independent 96 kB memory banks
Table 9. LPC3152/3154 boot modes
Boot mode GPIO0 GPIO1 GPIO2 Description
NAND 0 0 0 Boots from NAND flash. If proper image is not found,
boot ROM will switch to DFU boot mode.
SPI 0 0 1 Boot from SPI NOR flash connected to SPI_CS_OUT0. If
proper image is not found, boot ROM will switch to DFU
boot mode.
DFU 0 1 0 Device boots via USB using DFU class specification.
SD/MMC 0 1 1 Boot ROM searches all the partitions on the
SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.
If partition table is missing, it will start searching from
sector 0. A valid image is said to be found if a valid image
header is found, followed by a valid image. If a proper
image is not found, boot ROM will switch to DFU boot
mode.
Reserved 0 1 0 0 Reserved for testing.
NOR flash 1 0 1 Boot from parallel NOR flash connected to
EBI_NSTCS_1.
[1]
UART 1 1 0 Boot ROM tries to download boot image from UART
((115200 – 8 – n –1) assuming 12 MHz FFAST clock).
Test 1 1 1 Boot ROM is testing ISRAM using memory pattern test
and basic functionality of the analog audio block.
Switches to UART boot mode on receiving three ASCI
dots ("...") on UART.