Datasheet

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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 23 of 88
NXP Semiconductors
LPC3152/3154
• This module has its own, integrated DMA engine.
USB-IF TestID for Hi-speed peripheral silicon and embedded host silicon: 40720018
6.11 DMA controller
The DMA Controller can perform DMA transfers on the AHB bus without using the CPU.
This module has the following features:
• Supported transfer types:
Memory to memory copy:
– Memory can be copied from the source address to the destination address with a
specified length, while incrementing the address for both the source and
destination.
Memory to peripheral:
– Data is transferred from incrementing memory to a fixed address of a peripheral.
The flow is controlled by the peripheral.
Peripheral to memory:
– Data is transferred from a fixed address of a peripheral to incrementing memory.
The flow is controlled by the peripheral.
• Supports single data transfers for all transfer types.
• Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
• The DMA controller has 12 channels.
• Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
• Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.
• Compatible with ARM flow control, for single requests, last single requests, terminal
count info, and dma clearing.
• Supports swapping in endianess of the transported data.
[1] AES decryption engine is available on LPC3154 only.
Table 10: Peripherals that support DMA access
Peripheral name Supported Transfer Types
NAND flash controller/AES decryption engine
[1]
Memory to memory
SPI Memory to peripheral and peripheral to memory
MCI Memory to peripheral and peripheral to memory
LCD Interface Memory to peripheral
UART Memory to peripheral and peripheral to memory
I
2
C0/1-bus interfaces Memory to peripheral and peripheral to memory
I
2
S0/1 receive input Peripheral to memory
I
2
S0/1 transmit output Memory to peripheral
PCM interface Memory to peripheral and peripheral to memory