Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 24 of 88
NXP Semiconductors
LPC3152/3154
6.12 Interrupt controller
The interrupt controller collects interrupt requests from multiple devices, masks interrupt
requests, and forwards the combined requests to the processor. The interrupt controller
also provides facilities to identify the interrupt requesting devices to be served.
This module has the following features:
• The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
• Two interrupt lines (Fast Interrupt Request (FIQ) and Interrupt Request (IRQ)) to the
ARM core. The ARM core supports two distinct levels of priority on all interrupt
sources, FIQ for high priority interrupts and IRQ for normal priority interrupts.
• Software interrupt request capability associated with each request input.
• Visibility of interrupts request state before masking.
• Support for nesting of interrupt service routines.
• Interrupts routed to IRQ and to FIQ are vectored.
• Level interrupt support.
The following blocks can generate interrupts:
• NAND flash controller
• USB 2.0 HS OTG
• Event router
• 10 bit ADC
• UART
• LCD int
• MCI
• SPI
• I
2
C0-bus and I
2
C1-bus
• Timer 0, timer 1, timer 2, and timer 3
• I
2
S transmit: I2STX_0 and I2STX_1
• I
2
S receive: I2SRX_0 and I2SRX_1
• DMA
6.13 Multi-layer AHB
The multi-layer AHB is an interconnection scheme, based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.
Multiple masters can have access to different slaves at the same time.
Figure 5
gives an overview of the multi-layer AHB configuration in the LPC3152/3154.
AHB masters and slaves are numbered according to their AHB port number.