Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 25 of 88
NXP Semiconductors
LPC3152/3154
This module has the following features:
(1) AES decryption engine is available on LPC3154 only.
Fig 5. LPC3152/3154 AHB multi-layer matrix connections
master
= master/slave connection supported by matrix
002aae080
USB-OTG
AHB
MASTER
3
0
DMA
2
I-CACHE
D-CACHE
1
ARM
926EJ-S
AHB-APB
BRIDGE 0
AHB-APB
BRIDGE 1
AHB-APB
BRIDGE 3
AHB-APB
BRIDGE 4
NAND CONTROLLER
INTERRUPT CONTROLLER
PWM
I
2
C1I
2
C0
TIMER 0
10-bit ADC
CGU
WDT
SYSTEM CONTROL
IOCONFIG
EVENT ROUTER
RNG
OTP
I
2
S0/1
NAND REGISTERS
DMA REGISTERS
TIMER 1 TIMER 2 TIMER 3
AHB-APB
BRIDGE 2
UARTLCD SPIPCM
slave
MULTI-LAYER AHB MATRIX
0
1
2
3
4
5
MCI SD/SDIO
7
USB HIGH-SPEED OTG
8
ISRAM 0
9
ISRAM 1
10
ISROM
11
MPMC CONFIG
MPMC CONTROLLER
13
12
6
0
0
123
0123
5467
01 23456
01
AES
(1)
BUFFER