Datasheet

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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 26 of 88
NXP Semiconductors
LPC3152/3154
• Supports all combinations of 32-bit masters and slaves (fully connected interconnect
matrix).
• Round-Robin priority mechanism for bus arbitration: all masters have the same
priority and get bus access in their natural order
• Four devices on a master port (listed in their natural order for bus arbitration):
– DMA
– ARM926 instruction port
– ARM926 data port
– USB OTG
• Devices on a slave port (some ports are shared between multiple devices):
– AHB to APB Bridge 0
– AHB to APB Bridge 1
– AHB to APB Bridge 2
– AHB to APB Bridge 3
– AHB to APB Bridge 4
– Interrupt controller
– NAND flash controller
– MCI SD/SDIO
– USB 2.0 HS OTG
– 96 kB ISRAM0
– 96 kB ISRAM1
– 128 kB ROM
– MPMC (Multi-Purpose Memory Controller)
6.14 APB bridge
The APB Bridge is a bus bridge between AMBA Advanced High-performance Bus (AHB)
and the ARM Peripheral Bus (APB) interface.
The module supports two different architectures:
• Single Clock Architecture, synchronous bridge. The same clock is used at the AHB
side and at the APB side of the bridge. The AHB-to-APB4 bridge uses this
architecture.
• Dual Clock Architecture, asynchronous bridge. Different clocks are used at the AHB
side and at the APB side of the bridge. The AHB-to-APB0, AHB-to-APB1,
AHB-to-APB2, and AHB-to-APB3 bridges use this architecture.
6.15 Clock Generation Unit (CGU)
The clock generation unit generates all clock signals in the system and controls the reset
signals for all modules.
The structure of the CGU is shown in Figure 6
. Each output clock generated by the CGU
belongs to one of the domains. Each clock domain is fed by a single base clock that
originates from one of the available clock sources. Within a clock domain, fractional
dividers are available to divide the base clock to a lower frequency.