Datasheet

DR
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D
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DRA
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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 27 of 88
NXP Semiconductors
LPC3152/3154
Within most clock domains, the output clocks are again grouped into one or more
subdomains. All output clocks within one subdomain are either all generated by the same
fractional divider or they are connected directly to the base clock. Therefore all output
clocks within one subdomain have the same frequency and all output clocks within one
clock domain are synchronous because they originate from the same base clock
The CGU reference clock is generated by the external crystal. Furthermore the CGU has
several Phase Locked Loop (PLL) circuits to generate clock signals that can be used for
system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can
be used as reference input for the PLLs.
This module has the following features:
• Advanced features to optimize the system for low power:
– All output clocks can be disabled individually for flexible power optimization
– Some modules have automatic clock gating: they are only active when (bus)
access to the module is required.
– Variable clock scaling for automatic power optimization of the AHB bus (high clock
frequency when the bus is active, low clock frequency when the bus is idle).
– Clock wake-up feature: module clocks can be programmed to be activated
automatically on the basis of an event detected by the Event Router (see also
Section 6.19
). For example, all clocks (including the ARM /bus clocks) are off and
activated automatically when a button is pressed.
• Supports three clock sources:
– Reference clock generated by the oscillator with an external crystal.
– Pins I2SRX_BCK0, I2SRX_WS0 are used to input external clock signals (used for
generating audio frequencies in I
2
S receive / I
2
S transmit slave mode, see also
Section 6.4
).
• Two PLLs:
– System PLL generates programmable system clock frequency from its reference
input.
– Audio PLL generates programmable audio clock frequency (typically 256 × fs) from
its reference input.
Remark: Both the System PLL and the audio PLL generate their frequencies
based on their (individual) reference clocks. The reference clocks can be
programmed to the oscillator clock or one of the external clock signals.
• Highly flexible switchbox to distribute the signals from the clock sources to the module
clocks.
– Each clock generated by the CGU is derived from one of the base clocks and
optionally divided by a fractional divider.
– Each base clock can be programmed to have any one of the clock sources as an
input clock.
– Fractional dividers can be used to divide a base clock by a fractional number to a
lower clock frequency.
– Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
output clock.
• Register interface to reset all modules under software control.