Datasheet

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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 28 of 88
NXP Semiconductors
LPC3152/3154
• Based on the input of the Watchdog timer (see also Section 6.16), the CGU can
generate a system-wide reset in the case of a system stall.
6.16 Watchdog Timer (WDT)
The Watchdog Timer can be used to generate a system reset if there is a CPU/software
crash. In addition the watchdog timer can be used as an ordinary timer. Figure 7
shows
how the Watchdog Timer module is connected in the system.
This module has the following features:
• In the event of a software or hardware failure, generates a chip-wide reset request
when its programmed time-out period has expired (output m1).
• Watchdog counter can be reset by a periodical software trigger.
• After a reset, a register will indicate whether a reset has occurred because of a
watchdog generated reset.
• Watchdog timer can also be used as a normal timer in addition to the watchdog
functionality (output m0).
The LPC3152/3154 has 11 clock domains (n = 11). The number of fractional dividers depends on the clock domain.
Fig 6. CGU block diagram
OSCILLATOR
I2SRX_BCK0
I2SRX_WS0
BASE
BASE
I
2
S/AUDIO
PLL
EXTERNAL
CRYSTAL
SYSTEM
PLL
002aae385
CLOCK DOMAIN 0
CLOCK DOMAIN n
FRACTIONAL
DIVIDER 0
FRACTIONAL
DIVIDER i
FRACTIONAL
DIVIDER 6
FRACTIONAL
DIVIDER j
clock resources clock outputs
SWITCHBOX
subdomain clocks
to modules