Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 38 of 88
NXP Semiconductors
LPC3152/3154
Figure 9 only shows the signals that are involved in pad-muxing, so not all interface
signals are visible.
The EBI unit between the NAND flash interface and the MPMC contains an arbiter that
determines which interface is muxed to the outside world. Both NAND flash and
SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin
arbitration (see Section 6.6
).
6.28.3 Supply domains
As is shown in Figure 9 the EBI (NAND flash/MPMC-control/data) is connected to a
different supply domain than the LCD interface. The EBI control and address signals are
muxed with the LCD interface signals and are part of supply domain SUP8. The
SDRAM/SRAM data lines are shared with the NAND flash through the EBI and are part of
supply domain SUP4. Therefore the following rules apply for connecting memories:
1. SDRAM and bus-based LCD or SRAM: This is the MPMC mode. The supply voltage
for SDRAM/SRAM/bus-based LCD and NAND flash must be the same.The dedicated
LCD interface is not available in this MPMC mode.
Fig 9. Diagram of LCD and MPMC multiplexing
NAND_RYBN[0:3]
NAND_NCS_[0:3]
NAND
FLASH
INTERFACE
control
control
control
data
LCD_DB_[1:0],
control
control
control
(ALE, CLE)
EBI_A_0_ALE
EBI_A_1_CLE
EBI
2
16
data
2
6
data
16
address
EBI_A_[15:2]
14
14
data
LCD_DB_[15:2]
14
6
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
EBI_DQM_0_NOE
LCD_CSB/EBI_NSTCS_0
LCD_DB_1/EBI_NSTCS_1
LCD_DB_0/EBI_CLKOUT
LCD_E_RD/EBI_CKE
LCD_RS/EBI_NDYCS
LCD_RW_WR/EBI_DQM_1
LCD_DB_[15:2] (LCD mode)/
EBI_A_[15:2] (MPMC mode)
EBI_D_[15:0]
16
data
16
address
MPMC
LCD
address
EBI_A_[1:0]
2
6
3
SYSCREG_MUX_LCD_EBI_SEL
register
(I/O multplexing)
MPMC
mode
LCD
mode
LPC31xx
002aae157
SUP4
SUP8
0
1
0
1