Datasheet

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LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 39 of 88
NXP Semiconductors
LPC3152/3154
2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage
(SUP4) can be different from the LCD supply voltage (SUP8).
6.29 Timer module
The LPC3152/3154 contains four fully independent timer modules, which can be used to
generate interrupts after a pre-set time interval has elapsed.
This module has the following features:
• Each timer is a 32 bit wide down-counter with selectable pre-scale. The pre-scaler
allows using either the module clock directly or the clock divided by 16 or 256.
• Two modes of operation:
– Free-running timer: The timer generates an interrupt when the counter reaches
zero. The timer wraps around to 0xFFFF FFFF and continues counting down.
– Periodic timer: The timer generates an interrupt when the counter reaches zero. It
reloads the value from a load register and continues counting down from that
value. An interrupt will be generated every time the counter reaches zero. This
effectively gives a repeated interrupt at a regular interval.
• At any time the current timer value can be read.
• At any time the value in the load register may be re-written, causing the timer to
restart.
6.30 Pulse Width Modulation (PWM) module
This PWM can be used to generate a pulse width modulated or a pulse density modulated
signal. With an external low pass filter, the module can be used to generate a low frequent
analog signal. A typical use of the output of the module is to control the backlight of an
LCD display.
This module has the following features:
• Supports Pulse Width Modulation (PWM) with software controlled duty cycle.
• Supports Pulse Density Modulation (PDM) with software controlled pulse density.
6.31 System control registers
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
6.32 Audio Subsystem (ADSS)
The audio subsystem consists of the following blocks:
• I
2
S interfaces on the digital die (see Section 6.32.1):
– I
2
S0 digital audio input/output (I2SRX_0/I2STX_0)
– I
2
S1 (I2SRX_1/I2STX_1) interface to the audio analog block (I
2
S1 signals not
pinned out)
– Edge detector