Datasheet

DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
F
T DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
F
T DRAFT DRAFT DRAFT DRA
LPC3152_3154 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 0.12 — 27 May 2010 4 of 88
NXP Semiconductors
LPC3152/3154
4. Block diagram
(1) AES decryption engine available in LPC3154 only.
Fig 1. LPC3152/3154 block diagram
96 kB ISRAM0
ARM926EJ-S
TEST/DEBUG
INTERFACE
DMA
MCI
SD/SDIO
USB 2.0
HIGH-SPEED
OTG
AHB TO
APB
BRIDGE 0
JTAG
WDT
SYSTEM
CONTROL
CGU
IOCONFIG
10-bit ADC
RNG
EVENT
ROUTER
OTP
LPC3152/3154
master
mastermaster
master slave
002aae095
slave
AHB TO
APB
BRIDGE 1
I
2
C1
PWM
I
2
C0
TIMER 0/1/2/3
slave
NAND
REGISTERS
DMA
REGISTERS
AHB TO
APB
BRIDGE 4
slave
slave
96 kB ISRAM1
slave
slave
ROM
INTERRUPT
CONTROLLER
slave
slave
slave
slave
slave
MULTI-LAYER AHB MATRIX
DATA
CACHE 16 kB
INSTRUCTION
CACHE 16 kB
UART
LCD
SPI
PCM
AHB TO
APB
BRIDGE 2
MPMC
I
2
S0
AHB TO
APB
BRIDGE 3
slave slave
I
2
S1
RTC
PSU
Li-ION
CHARGER
ANALOG
DIE
AUDIO
CODEC
USB
CHARGE
PUMP
NAND
CONTROLLER
BUFFER
AES
(1)